conta_10s_estrutural

library IEEE;
use ieee.std_logic_1164.all;

entity conta_10s is
port (clock, reset: in std_logic;
        HEX0: out std_logic_vector (0 to 6));
end conta_10s;

architecture arquitetura of conta_10s is

    component display_vetores is
    port (bcd: in std_logic_vector (3 downto 0);
              HEX0: out std_logic_vector (0 to 6));
    end component;

    component divisor_clk is
    port (clk_in: in std_logic;
              q: out std_logic);
    end component;

    component conta_decada is
    port (clk:in std_logic;
         reset: in std_logic;
         q: out std_logic_vector(3 downto 0));
    end component;

    signal chupitilha: std_logic;
    signal querrenca: std_logic_vector (3 downto 0);

begin
talita: divisor_clk port map (clock, chupitilha);
feliperenato: conta_decada port map (chupitilha, reset, querrenca);
caleb: display_vetores port map (querrenca, HEX0);

end arquitetura;