Lab #1 - VHDL (Dean Nguyen)

--Lab #1: Logical AND (Dean Nguyen)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.NUMERIC_STD.ALL;

ENTITY logical_and IS
    PORT(   a, b    : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
            z       : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END logical_and;

ARCHITECTURE behavioral OF logical_and IS
BEGIN
    z <= a and b;
END behavioral;

--Lab #1: Logical OR (Dean Nguyen)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.NUMERIC_STD.ALL;

ENTITY logical_or IS
    PORT(   a, b    : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
            z       : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END logical_or;

ARCHITECTURE behavioral OF logical_or IS
BEGIN
    z <= a or b;
END behavioral;

--Lab #1: Logical XOR (Dean Nguyen)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.NUMERIC_STD.ALL;

ENTITY logical_xor IS
    PORT(   a, b    : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
            z       : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END logical_xor;

ARCHITECTURE behavioral OF logical_xor IS
BEGIN
    z <= a xor b;
END behavioral;

--Lab #1: Shift Right Arithmetic (Dean Nguyen)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.NUMERIC_STD.ALL;

ENTITY shift_right_arithmetic IS
    PORT(   din : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
            numin   : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
            dout    : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END shift_right_arithmetic;

ARCHITECTURE behavioral OF shift_right_arithmetic IS
SIGNAL shift_signed_r   : SIGNED(3 DOWNTO 0);
SIGNAL num_shift            : INTEGER;
BEGIN
    num_shift <= to_integer(unsigned(numin));
    shift_signed_r <= shift_right(signed(din), num_shift);
    dout <= std_logic_vector(shift_signed_r);
END behavioral;

--Lab #1: Shift Right Logical (Dean Nguyen)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.NUMERIC_STD.ALL;

ENTITY shift_right_logical IS
    PORT(   din : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
            numin   : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
            dout    : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END shift_right_logical;

ARCHITECTURE behavioral OF shift_right_logical IS
SIGNAL shift_signed_r   : UNSIGNED(3 DOWNTO 0);
SIGNAL num_shift            : INTEGER;
BEGIN
    num_shift <= to_integer(unsigned(numin));
    shift_signed_r <= shift_right(unsigned(din), num_shift);
    dout <= std_logic_vector(shift_signed_r);
END behavioral;

--Lab #1: ALU (Dean Nguyen)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.NUMERIC_STD.ALL;

ENTITY ALU IS
    PORT( Operand1, Operand2, OPCODE    : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
            Result                          : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END ALU;

ARCHITECTURE structural OF ALU IS

COMPONENT logical_and
    PORT(   a, b    : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
            z       : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END COMPONENT;

COMPONENT logical_or
    PORT(   a, b    : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
            z       : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END COMPONENT;

COMPONENT logical_xor
    PORT(   a, b    : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
            z       : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END COMPONENT;

COMPONENT shift_right_arithmetic
    PORT(   din : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
            numin   : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
            dout    : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END COMPONENT;

COMPONENT shift_right_logical
    PORT(   din : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
            numin   : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
            dout    : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END COMPONENT;

SIGNAL result_reg_and, result_reg_or, result_reg_xor, result_reg_srl, result_reg_sra    : STD_LOGIC_VECTOR(3 DOWNTO 0);

BEGIN

log_and     : logical_and   PORT MAP(   a => Operand1, b => Operand2, z => result_reg_and);
log_or  : logical_or    PORT MAP(   a => Operand1, b => Operand2, z => result_reg_or);
log_xor : logical_xor   PORT MAP(   a => Operand1, b => Operand2, z => result_reg_xor);
s_ra        : shift_right_arithmetic    PORT MAP(   din => Operand1, numin => Operand2, dout => result_reg_sra);
s_rl        : shift_right_logical       PORT MAP(   din => Operand1, numin => Operand2, dout => result_reg_srl);

    PROCESS(OPCODE)
    BEGIN
        CASE OPCODE IS
            WHEN "1000" =>
                Result <= result_reg_or;
            WHEN "1010" =>
                Result <= result_reg_and;
            WHEN "1011" =>
                Result <= result_reg_xor;
            WHEN "1101" =>
                Result <= result_reg_srl;
            WHEN "1110" =>
                Result <= result_reg_sra;
            WHEN OTHERS =>
                Result <= "0000";
        END CASE;
    END PROCESS;
END structural;

--Lab #1: ALU_TB (Dean Nguyen)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.NUMERIC_STD.ALL;

ENTITY ALU_TB IS
END ALU_TB;

ARCHITECTURE behavioral OF ALU_TB IS
COMPONENT ALU
    PORT( Operand1, Operand2, OPCODE    : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
            Result                          : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END COMPONENT;

--Inputs--
SIGNAL Op1_TB : STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
SIGNAL Op2_TB : STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
SIGNAL Code_TB : STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
--Outputs--
SIGNAL Result_TB : STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');

BEGIN
    uut: ALU PORT MAP (
        Operand1 => Op1_TB,
        Operand2 => Op2_TB,
        OPCODE => Code_TB,
        Result => Result_TB);

    stimulus : PROCESS
    BEGIN
        FOR i IN 0 TO 15 LOOP
            Code_TB <= STD_LOGIC_VECTOR(to_unsigned(i, 4));
            IF ((i = 8) or (i = 10) or (i = 11) or (i = 13) or (i = 14)) THEN
                FOR j IN 0 TO 15 LOOP
                    Op1_TB <= STD_LOGIC_VECTOR(to_unsigned(j, 4));
                        FOR k IN 0 TO 15 LOOP
                            Op2_TB <= STD_LOGIC_VECTOR(to_unsigned(k, 4));
                            WAIT for 100 ns;
                        END LOOP;
                END LOOP;
            ELSE
                NEXT;
            END IF;
        END LOOP;
        WAIT;
    END PROCESS;
END behavioral;