library ieee;
use ieee.std_logic_1164.all;

entity TTL74198 is
    port(
        CLK, CLEAR, Din_r, Din_l    : in std_logic;
        Din_p   : in std_logic_vector(7 downto 0);
        S : in std_logic_vector(1 downto 0);
        Q : out std_logic_vector(7 downto 0)
    );
end TTL74198;

architecture TTL74198 of TTL74198 is
    signal reg1: std_logic_vector(7 downto 0);
    begin
        process(CLK, CLEAR)

            begin
                if CLEAR = '0' then
                    reg1 <= (others => '0');
                elsif CLK'event and CLK = '1' then
                    case S is
                        when "01" =>
                            reg1 <= Din_r & reg1(7 downto 1);
                        when "10" =>
                            reg1 <= reg1(6 downto 0) & Din_l;
                        when "11" =>
                            reg1 <= Din_p;
                        when others =>
                            null;
                    end case;
                end if;
        end process;

        Q <= reg1;
end TTL74198;