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Aug 27th, 2025
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  1. // SPI peripheral setup
  2. Baudrate: DIV128 (HSI 16MHz -> 125kHz)
  3. Clock polarity: Low on idle
  4. Clock phase: First transition
  5. DDF: 8 bits
  6. FF: MSB first
  7. SSI and SSM: enabled
  8. Frame std: Motorola
  9. Role: Master
  10.  
  11. // This is the init sequence
  12. delay_ms(1000);
  13.  
  14. cs_high();
  15. for (u32 i = 0; i < 30; ++i)
  16. {
  17.   WAIT_UNTIL(spi_is_flag_set(SPI1, SPI_FLAG_TX_BUF_EMPTY));
  18.   spi_data_write(SPI1, 0xff);
  19. }
  20.  
  21. u8 cmd0[] = {
  22.   0x40, 0x00, 0x00, 0x00, 0x00, 0x95
  23. };
  24.  
  25. cs_low();
  26. send_spi_cmd(cmd0);
  27. u8 r1 = get_spi_resp();
  28. cs_high();
  29.  
  30. if (r1 != 0x01)
  31. {
  32.   while (1);
  33. }
  34.  
  35. u8 cmd8[] = {
  36.   0x48, 0x00, 0x00, 0x01, 0xaa, 0x87
  37. };
  38.  
  39. cs_low();
  40.  
  41. send_spi_cmd(cmd8);
  42. r1 = get_spi_resp();
  43. u32 r7[4];
  44. for (u32 i = 0; i < 4; ++i)
  45. {
  46.   spi_data_write(SPI1, 0xff);
  47.   WAIT_UNTIL(spi_is_flag_set(SPI1, SPI_FLAG_RX_BUF_NOT_EMPTY));
  48.   WAIT_UNTIL(spi_is_flag_set(SPI1, SPI_FLAG_BUSY) == 0);
  49.   r7[i] = spi_data_read(SPI1);
  50. }
  51.  
  52. cs_high();
  53. // r7 = 0x00, 0x00, 0x01, 0xaa
  54.  
  55. u8 cmd58[] = { 0x7a, 0x00, 0x00, 0x00, 0x00, 0xfd };
  56.  
  57. cs_low();
  58. send_spi_cmd(cmd58);
  59. r1 = get_spi_resp();
  60. u8 ocr[4];
  61. for (u32 i = 0; i < 4; ++i)
  62. {
  63.   spi_data_write(SPI1, 0xff);
  64.   WAIT_UNTIL(spi_is_flag_set(SPI1, SPI_FLAG_RX_BUF_NOT_EMPTY));
  65.   WAIT_UNTIL(spi_is_flag_set(SPI1, SPI_FLAG_BUSY) == 0);
  66.   ocr[i] = spi_data_read(SPI1);
  67. }
  68. cs_high();
  69. // OCR = 0x00, 0xff, 0x80, 0x00
  70.  
  71. u8 cmd55[] = { 0x77, 0x0, 0x0, 0x0, 0x0, 0x65 };
  72. u8 acmd41[] = { 0x69, 0x00, 0x00, 0x00, 0x00, 0x5f };
  73.  
  74. while (1)
  75. {
  76.   cs_low();
  77.   send_spi_cmd(cmd55);
  78.   u8 cmd55_r = get_spi_resp();
  79.   cs_high();
  80.  
  81.   if (cmd55_r != 0x01)
  82.   {
  83.     // Error
  84.     break;
  85.   }
  86.  
  87.   delay_ms(100);
  88.  
  89.   cs_low();
  90.   send_spi_cmd(acmd41);
  91.   u8 acmd41_r = get_spi_resp();
  92.   cs_high();
  93.  
  94.   if (acmd41_r == 0)
  95.   {
  96.     // Card is ready
  97.     break;
  98.   }
  99.  
  100.   delay_ms(100);
  101. }
  102.  
  103. // send_spi_cmd() and get_spi_resp()
  104. void
  105. send_spi_cmd(u8* cmd)
  106. {
  107.   for (u32 i = 0; i < 6; ++i)
  108.   {
  109.     WAIT_UNTIL(spi_is_flag_set(SPI1, SPI_FLAG_TX_BUF_EMPTY));
  110.     spi_data_write(SPI1, cmd[i]);
  111.  
  112.     WAIT_UNTIL(spi_is_flag_set(SPI1, SPI_FLAG_BUSY) == 0);
  113.  
  114.     WAIT_UNTIL(spi_is_flag_set(SPI1, SPI_FLAG_RX_BUF_NOT_EMPTY));
  115.     (void) spi_data_read(SPI1);
  116.   }
  117. }
  118.  
  119. u8
  120. get_spi_resp(void)
  121. {
  122.   while (1)
  123.   {
  124.     WAIT_UNTIL(spi_is_flag_set(SPI1, SPI_FLAG_TX_BUF_EMPTY));
  125.     spi_data_write(SPI1, 0xff);
  126.  
  127.     WAIT_UNTIL(spi_is_flag_set(SPI1, SPI_FLAG_RX_BUF_NOT_EMPTY));
  128.     u8 data = spi_data_read(SPI1);
  129.  
  130.     if ((data & 0x80) == 0)
  131.     {
  132.       return data;
  133.     }
  134.   }
  135. }
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