лампочка 1 сек

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_arith.all;

entity lab72 is
    Port (clk : in std_logic;
        dout : out std_logic_vector(7 downto 0));
end lab72;

architecture Behavioral of lab72 is
signal cntr : std_logic_vector(26 downto 0):=(others => '0');
signal sdout : std_logic_vector(7 downto 0):="00000000";
begin
process(clk) begin
    if rising_edge(clk) then
        cntr <= unsigned(cntr) +1;
        sdout(0) <=  cntr(26);
    end if;
end process;
dout <= sdout;
end Behavioral;