LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_unsigned.all ;

ENTITY MULTIPLY IS
PORT(MULTI_IN: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
    MULTI_OUT_1: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
    MULTI_OUT_2: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END ;

ARCHITECTURE MULTI_DEF OF MULTIPLY IS
    SIGNAL NUM1: STD_LOGIC_VECTOR(3 DOWNTO 0);
    SIGNAL NUM2: STD_LOGIC_VECTOR(3 DOWNTO 0);
    SIGNAL RESULT: STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
    NUM1 <= MULTI_IN(3 DOWNTO 0);
    NUM2 <= MULTI_IN(7 DOWNTO 4);
    RESULT <= NUM1*NUM2;
    MULTI_OUT_1 <= RESULT(3 DOWNTO 0);
    MULTI_OUT_2 <= RESULT(7 DOWNTO 4);
END MULTI_DEF;

Library Ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

ENTITY DRIVER_1 IS
PORT(DRIVER_IN: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
    DRIVER_OUT: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END;

ARCHITECTURE DRIVER_1_DEF OF DRIVER_1 IS
BEGIN
    DRIVER_OUT(0) <= ((NOT DRIVER_IN(2)) AND (NOT DRIVER_IN(0))) OR (DRIVER_IN(1) AND (NOT DRIVER_IN(0))) OR ((NOT DRIVER_IN(3)) AND DRIVER_IN(1)) OR (DRIVER_IN(2) AND DRIVER_IN(1)) OR ((NOT DRIVER_IN(3)) AND DRIVER_IN(2) AND DRIVER_IN(0)) OR (DRIVER_IN(3) AND (NOT DRIVER_IN(2)) AND (NOT DRIVER_IN(1))) OR ((NOT DRIVER_IN(1)) AND (NOT DRIVER_IN(0)) AND DRIVER_IN(3));
    DRIVER_OUT(1) <= ((NOT DRIVER_IN(3) AND (NOT DRIVER_IN(2)))) OR (NOT (DRIVER_IN(2)) AND (NOT DRIVER_IN(0))) OR ((NOT DRIVER_IN(2)) AND (NOT DRIVER_IN(3))) OR (DRIVER_IN(1) AND DRIVER_IN(0) AND (NOT DRIVER_IN(3))) OR ((NOT DRIVER_IN(1) AND DRIVER_IN(0) AND DRIVER_IN(3))) OR ((NOT DRIVER_IN(1)) AND (NOT DRIVER_IN(0)) AND (NOT DRIVER_IN(3)));
    DRIVER_OUT(2) <= (DRIVER_IN(3) AND (NOT DRIVER_IN(2))) OR ((NOT DRIVER_IN(3)) AND DRIVER_IN(2)) OR ((NOT DRIVER_IN(3)) AND DRIVER_IN(0)) OR ((NOT DRIVER_IN(1)) AND DRIVER_IN(0)) OR ((NOT DRIVER_IN(3)) AND (NOT DRIVER_IN(1)));
    DRIVER_OUT(3) <= ((NOT DRIVER_IN(2)) AND (NOT DRIVER_IN(0)) AND (NOT DRIVER_IN(3))) OR ((NOT DRIVER_IN(3)) AND (NOT DRIVER_IN(2)) AND DRIVER_IN(1)) OR (DRIVER_IN(1) AND (NOT DRIVER_IN(0)) AND DRIVER_IN(2)) OR ((NOT DRIVER_IN(1)) AND DRIVER_IN(0) AND DRIVER_IN(2)) OR (DRIVER_IN(3) AND (NOT DRIVER_IN(1)) AND (NOT DRIVER_IN(0))) OR (DRIVER_IN(1) AND DRIVER_IN(0) AND (NOT DRIVER_IN(2)));
    DRIVER_OUT(4) <= ((NOT DRIVER_IN(2)) AND (NOT DRIVER_IN(0))) OR (DRIVER_IN(1) AND (NOT DRIVER_IN(0))) OR (DRIVER_IN(3) AND DRIVER_IN(2)) OR (DRIVER_IN(3) AND (NOT DRIVER_IN(2)) AND DRIVER_IN(1));
    DRIVER_OUT(5) <= (DRIVER_IN(3) AND (NOT DRIVER_IN(2))) OR ((NOT DRIVER_IN(1)) AND (NOT DRIVER_IN(0))) OR ((NOT DRIVER_IN(3)) AND DRIVER_IN(2) AND (NOT DRIVER_IN(1))) OR (DRIVER_IN(3) AND DRIVER_IN(2) AND DRIVER_IN(1)) OR (DRIVER_IN(2) AND (NOT DRIVER_IN(0)));
    DRIVER_OUT(6) <= (DRIVER_IN(3) AND (NOT DRIVER_IN(2))) OR (DRIVER_IN(1) AND (NOT DRIVER_IN(0))) OR ((NOT DRIVER_IN(2)) AND DRIVER_IN(1)) OR ((NOT DRIVER_IN(3)) AND DRIVER_IN(2) AND (NOT DRIVER_IN(1))) OR (DRIVER_IN(3) AND DRIVER_in(0));
END DRIVER_1_DEF;

Library Ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

ENTITY DRIVER_2 IS
PORT(DRIVER_IN: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
    DRIVER_OUT: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END;

ARCHITECTURE DRIVER_2_DEF OF DRIVER_2 IS
BEGIN
    DRIVER_OUT(0) <= ((NOT DRIVER_IN(2)) AND (NOT DRIVER_IN(0))) OR (DRIVER_IN(1) AND (NOT DRIVER_IN(0))) OR ((NOT DRIVER_IN(3)) AND DRIVER_IN(1)) OR (DRIVER_IN(2) AND DRIVER_IN(1)) OR ((NOT DRIVER_IN(3)) AND DRIVER_IN(2) AND DRIVER_IN(0)) OR (DRIVER_IN(3) AND (NOT DRIVER_IN(2)) AND (NOT DRIVER_IN(1))) OR ((NOT DRIVER_IN(1)) AND (NOT DRIVER_IN(0)) AND DRIVER_IN(3));
    DRIVER_OUT(1) <= ((NOT DRIVER_IN(3) AND (NOT DRIVER_IN(2)))) OR (NOT (DRIVER_IN(2)) AND (NOT DRIVER_IN(0))) OR ((NOT DRIVER_IN(2)) AND (NOT DRIVER_IN(3))) OR (DRIVER_IN(1) AND DRIVER_IN(0) AND (NOT DRIVER_IN(3))) OR ((NOT DRIVER_IN(1) AND DRIVER_IN(0) AND DRIVER_IN(3))) OR ((NOT DRIVER_IN(1)) AND (NOT DRIVER_IN(0)) AND (NOT DRIVER_IN(3)));
    DRIVER_OUT(2) <= (DRIVER_IN(3) AND (NOT DRIVER_IN(2))) OR ((NOT DRIVER_IN(3)) AND DRIVER_IN(2)) OR ((NOT DRIVER_IN(3)) AND DRIVER_IN(0)) OR ((NOT DRIVER_IN(1)) AND DRIVER_IN(0)) OR ((NOT DRIVER_IN(3)) AND (NOT DRIVER_IN(1)));
    DRIVER_OUT(3) <= ((NOT DRIVER_IN(2)) AND (NOT DRIVER_IN(0)) AND (NOT DRIVER_IN(3))) OR ((NOT DRIVER_IN(3)) AND (NOT DRIVER_IN(2)) AND DRIVER_IN(1)) OR (DRIVER_IN(1) AND (NOT DRIVER_IN(0)) AND DRIVER_IN(2)) OR ((NOT DRIVER_IN(1)) AND DRIVER_IN(0) AND DRIVER_IN(2)) OR (DRIVER_IN(3) AND (NOT DRIVER_IN(1)) AND (NOT DRIVER_IN(0))) OR (DRIVER_IN(1) AND DRIVER_IN(0) AND (NOT DRIVER_IN(2)));
    DRIVER_OUT(4) <= ((NOT DRIVER_IN(2)) AND (NOT DRIVER_IN(0))) OR (DRIVER_IN(1) AND (NOT DRIVER_IN(0))) OR (DRIVER_IN(3) AND DRIVER_IN(2)) OR (DRIVER_IN(3) AND (NOT DRIVER_IN(2)) AND DRIVER_IN(1));
    DRIVER_OUT(5) <= (DRIVER_IN(3) AND (NOT DRIVER_IN(2))) OR ((NOT DRIVER_IN(1)) AND (NOT DRIVER_IN(0))) OR ((NOT DRIVER_IN(3)) AND DRIVER_IN(2) AND (NOT DRIVER_IN(1))) OR (DRIVER_IN(3) AND DRIVER_IN(2) AND DRIVER_IN(1)) OR (DRIVER_IN(2) AND (NOT DRIVER_IN(0)));
    DRIVER_OUT(6) <= (DRIVER_IN(3) AND (NOT DRIVER_IN(2))) OR (DRIVER_IN(1) AND (NOT DRIVER_IN(0))) OR ((NOT DRIVER_IN(2)) AND DRIVER_IN(1)) OR ((NOT DRIVER_IN(3)) AND DRIVER_IN(2) AND (NOT DRIVER_IN(1))) OR (DRIVER_IN(3) AND DRIVER_in(0));
END DRIVER_2_DEF;

Library Ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

ENTITY LAB_1 IS
PORT(SW: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
    HEX0: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
    HEX1: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END;

ARCHITECTURE LAB_1_STRUCT OF LAB_1 IS
    COMPONENT MULTIPLY IS
        PORT(MULTI_IN: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
            MULTI_OUT_1: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
            MULTI_OUT_2: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
    END COMPONENT;
    COMPONENT DRIVER_1 IS
        PORT(DRIVER_IN: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
            DRIVER_OUT: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
    END COMPONENT;
    COMPONENT DRIVER_2 IS
        PORT(DRIVER_IN: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
            DRIVER_OUT: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
    END COMPONENT;
    SIGNAL MULTI_TO_DRIVER_1: STD_LOGIC_VECTOR(3 DOWNTO 0);
    SIGNAL MULTI_TO_DRIVER_2: STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
    U0: MULTIPLY
        PORT MAP(SW, MULTI_TO_DRIVER_1, MULTI_TO_DRIVER_2);
    U1: DRIVER_1
        PORT MAP(MULTI_TO_DRIVER_1, HEX0);
    U2: DRIVER_2
        PORT MAP(MULTI_TO_DRIVER_2, HEX1);
END LAB_1_STRUCT;