testbench

module testbench(A,B,S,out);

input[15:0] A,B;
output[15:0] out,S;
reg[3:0] S;
wire[15:0] out;

integer i;

alu_16mod mod(out,A,B,S);
assign A = 8'b1111000011110000;
assign B = 8'b0000111100001111;

initial

for (i=0;i<16;i=i+1)

begin

S=i;

end

endmodule