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- /*
- * File: main.c
- * Author: Jonathan
- *
- * Created on January 9, 2023, 12:54 PM
- */
- // PIC18F14K50 Configuration Bit Settings
- // 'C' source line config statements
- // CONFIG1L
- #pragma config CPUDIV = NOCLKDIV// CPU System Clock Selection bits (No CPU System Clock divide)
- #pragma config USBDIV = OFF // USB Clock Selection bit (USB clock comes directly from the OSC1/OSC2 oscillator block; no divide)
- // CONFIG1H
- #pragma config FOSC = IRC // Oscillator Selection bits (Internal RC oscillator)
- #pragma config PLLEN = OFF // 4 X PLL Enable bit (PLL is under software control)
- #pragma config PCLKEN = ON // Primary Clock Enable bit (Primary clock enabled)
- #pragma config FCMEN = OFF // Fail-Safe Clock Monitor Enable (Fail-Safe Clock Monitor disabled)
- #pragma config IESO = OFF // Internal/External Oscillator Switchover bit (Oscillator Switchover mode disabled)
- // CONFIG2L
- #pragma config PWRTEN = OFF // Power-up Timer Enable bit (PWRT disabled)
- #pragma config BOREN = SBORDIS // Brown-out Reset Enable bits (Brown-out Reset enabled in hardware only (SBOREN is disabled))
- #pragma config BORV = 19 // Brown-out Reset Voltage bits (VBOR set to 1.9 V nominal)
- // CONFIG2H
- #pragma config WDTEN = OFF // Watchdog Timer Enable bit (WDT is controlled by SWDTEN bit of the WDTCON register)
- #pragma config WDTPS = 32768 // Watchdog Timer Postscale Select bits (1:32768)
- // CONFIG3H
- #pragma config HFOFST = ON // HFINTOSC Fast Start-up bit (HFINTOSC starts clocking the CPU without waiting for the oscillator to stablize.)
- #pragma config MCLRE = ON // MCLR Pin Enable bit (MCLR pin enabled; RA3 input pin disabled)
- // CONFIG4L
- #pragma config STVREN = ON // Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset)
- #pragma config LVP = OFF // Single-Supply ICSP Enable bit (Single-Supply ICSP disabled)
- #pragma config BBSIZ = OFF // Boot Block Size Select bit (1kW boot block size)
- #pragma config XINST = OFF // Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode))
- // CONFIG5L
- #pragma config CP0 = OFF // Code Protection bit (Block 0 not code-protected)
- #pragma config CP1 = OFF // Code Protection bit (Block 1 not code-protected)
- // CONFIG5H
- #pragma config CPB = OFF // Boot Block Code Protection bit (Boot block not code-protected)
- #pragma config CPD = OFF // Data EEPROM Code Protection bit (Data EEPROM not code-protected)
- // CONFIG6L
- #pragma config WRT0 = OFF // Table Write Protection bit (Block 0 not write-protected)
- #pragma config WRT1 = OFF // Table Write Protection bit (Block 1 not write-protected)
- // CONFIG6H
- #pragma config WRTC = OFF // Configuration Register Write Protection bit (Configuration registers not write-protected)
- #pragma config WRTB = OFF // Boot Block Write Protection bit (Boot block not write-protected)
- #pragma config WRTD = OFF // Data EEPROM Write Protection bit (Data EEPROM not write-protected)
- // CONFIG7L
- #pragma config EBTR0 = OFF // Table Read Protection bit (Block 0 not protected from table reads executed in other blocks)
- #pragma config EBTR1 = OFF // Table Read Protection bit (Block 1 not protected from table reads executed in other blocks)
- // CONFIG7H
- #pragma config EBTRB = OFF // Boot Block Table Read Protection bit (Boot block not protected from table reads executed in other blocks)
- // #pragma config statements should precede project file includes.
- // Use project enums instead of #define for ON and OFF.
- #define _XTAL_FREQ 1000000 //CPU clock frequency
- #include <xc.h> //Include general header file
- void main(void) //Main function of the program
- {
- TRISCbits.TRISC0 = 0; //Configure RC0 pin as output TRIS is the command. C is for the register. TRISC0 means IO Port 0. =0 sets it as output
- while (1) //Main loop of the program
- {
- LATCbits.LATC0 ^= 0x01;//Toggle RC0 pin
- __delay_ms(500); //500ms delay
- } //End of while loop
- } //End of void main(void)
- //Reference https://www.circuitbread.com/tutorials/embedded-c-programming-with-the-pic18f14k50-2-our-first-program
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