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  1. Index: src/southbridge/intel/i82371eb/i82371eb_fadt.c
  2. ===================================================================
  3. --- src/southbridge/intel/i82371eb/i82371eb_fadt.c      (revision 0)
  4. +++ src/southbridge/intel/i82371eb/i82371eb_fadt.c      (revision 0)
  5. @@ -0,0 +1,174 @@
  6. +/*
  7. + * This file is part of the coreboot project.
  8. + *
  9. + * Copyright (C) 2004 Nick Barker <nick.barker9@btinternet.com>
  10. + * Copyright (C) 2007, 2009 Rudolf Marek <r.marek@assembler.cz>
  11. + *
  12. + * This program is free software; you can redistribute it and/or modify
  13. + * it under the terms of the GNU General Public License as published by
  14. + * the Free Software Foundation; either version 2 of the License, or
  15. + * (at your option) any later version.
  16. + *
  17. + * This program is distributed in the hope that it will be useful,
  18. + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19. + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20. + * GNU General Public License for more details.
  21. + *
  22. + * You should have received a copy of the GNU General Public License
  23. + * along with this program; if not, write to the Free Software
  24. + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  25. + */
  26. +
  27. +#include <string.h>
  28. +#include <arch/acpi.h>
  29. +#include <device/device.h>
  30. +#include <device/pci.h>
  31. +#include <device/pci_ids.h>
  32. +//#include "vt8237r.h"
  33. +
  34. +/**
  35. + * Create the Fixed ACPI Description Tables (FADT) for any board with this SB.
  36. + */
  37. +void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
  38. +{
  39. +       acpi_header_t *header = &(fadt->header);
  40. +       device_t dev;
  41. +//     int is_vt8237s = 0;
  42. +
  43. +       /* Power management controller */
  44. +//     dev = dev_find_device(PCI_VENDOR_ID_VIA,
  45. +//                             PCI_DEVICE_ID_VIA_VT8237S_LPC, 0);
  46. +       dev = dev_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_SMB_ACPI, 0); // pci_ids.h
  47. +
  48. +//     if (dev)
  49. +//             is_vt8237s = 1;
  50. +
  51. +       memset((void *) fadt, 0, sizeof(acpi_fadt_t));
  52. +       memcpy(header->signature, "FACP", 4);
  53. +       header->length = 244;
  54. +       header->revision = 4;
  55. +       memcpy(header->oem_id, "COREBO", 6);
  56. +       memcpy(header->oem_table_id, "COREBOOT", 8);
  57. +       memcpy(header->asl_compiler_id, "CORE", 4);
  58. +       header->asl_compiler_revision = 42;
  59. +
  60. +       fadt->firmware_ctrl = (u32)facs;
  61. +       fadt->dsdt = (u32)dsdt;
  62. +       fadt->preferred_pm_profile = 0;
  63. +       fadt->sci_int = 9;
  64. +       fadt->smi_cmd = 0;
  65. +       fadt->acpi_enable = 0;
  66. +       fadt->acpi_disable = 0;
  67. +       fadt->s4bios_req = 0x0;
  68. +       fadt->pstate_cnt = 0x0;
  69. +
  70. +//     fadt->pm1a_evt_blk = VT8237R_ACPI_IO_BASE;
  71. +       fadt->pm1b_evt_blk = 0x0;
  72. +//     fadt->pm1a_cnt_blk = VT8237R_ACPI_IO_BASE + 0x4;
  73. +       fadt->pm1b_cnt_blk = 0x0;
  74. +       /* once we support C2/C3 this could be set to 0x22 and chipset needs to be adjusted too */
  75. +       fadt->pm2_cnt_blk = 0x0;
  76. +//     fadt->pm_tmr_blk = VT8237R_ACPI_IO_BASE + 0x8;
  77. +//     fadt->gpe0_blk = VT8237R_ACPI_IO_BASE + 0x20;
  78. +//     if (is_vt8237s) {
  79. +//             fadt->gpe1_blk = VT8237R_ACPI_IO_BASE + 0x60;
  80. +//             fadt->gpe1_base = 0x10;
  81. +//             fadt->gpe1_blk_len = 4;
  82. +//     } else {
  83. +               fadt->gpe1_blk = 0x0;
  84. +               fadt->gpe1_base = 0;
  85. +               fadt->gpe1_blk_len = 0;
  86. +//     }
  87. +
  88. +       fadt->pm1_evt_len = 4;
  89. +       fadt->pm1_cnt_len = 2;
  90. +       fadt->pm2_cnt_len = 0;
  91. +       fadt->pm_tmr_len = 4;
  92. +       fadt->gpe0_blk_len = 4;
  93. +
  94. +       fadt->cst_cnt = 0;
  95. +       fadt->p_lvl2_lat = 90;
  96. +       fadt->p_lvl3_lat = 900;
  97. +       fadt->flush_size = 0;
  98. +       fadt->flush_stride = 0;
  99. +       fadt->duty_offset = 0;
  100. +       fadt->duty_width = 1;   //??
  101. +       fadt->day_alrm = 0x7d;
  102. +       fadt->mon_alrm = 0x7e;
  103. +       fadt->century = 0x32;
  104. +       /* We have legacy devices, 8042, VGA is ok to probe, MSI are not supported */
  105. +       fadt->iapc_boot_arch = 0xb;
  106. +       /* check me */
  107. +       fadt->flags = 0xa5;
  108. +
  109. +       fadt->reset_reg.space_id = 0;
  110. +       fadt->reset_reg.bit_width = 0;
  111. +       fadt->reset_reg.bit_offset = 0;
  112. +       fadt->reset_reg.resv = 0;
  113. +       fadt->reset_reg.addrl = 0x0;
  114. +       fadt->reset_reg.addrh = 0x0;
  115. +
  116. +       fadt->reset_value = 0;
  117. +       fadt->x_firmware_ctl_l = (u32)facs;
  118. +       fadt->x_firmware_ctl_h = 0;
  119. +       fadt->x_dsdt_l = (u32)dsdt;
  120. +       fadt->x_dsdt_h = 0;
  121. +
  122. +       fadt->x_pm1a_evt_blk.space_id = 1;
  123. +       fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8;
  124. +       fadt->x_pm1a_evt_blk.bit_offset = 0;
  125. +       fadt->x_pm1a_evt_blk.resv = 0;
  126. +       fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk;
  127. +       fadt->x_pm1a_evt_blk.addrh = 0x0;
  128. +
  129. +       fadt->x_pm1b_evt_blk.space_id = 1;
  130. +       fadt->x_pm1b_evt_blk.bit_width = fadt->pm1_evt_len * 8;
  131. +       fadt->x_pm1b_evt_blk.bit_offset = 0;
  132. +       fadt->x_pm1b_evt_blk.resv = 0;
  133. +       fadt->x_pm1b_evt_blk.addrl = fadt->pm1b_evt_blk;
  134. +       fadt->x_pm1b_evt_blk.addrh = 0x0;
  135. +
  136. +       fadt->x_pm1a_cnt_blk.space_id = 1;
  137. +       fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8;
  138. +       fadt->x_pm1a_cnt_blk.bit_offset = 0;
  139. +       fadt->x_pm1a_cnt_blk.resv = 0;
  140. +       fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk;
  141. +       fadt->x_pm1a_cnt_blk.addrh = 0x0;
  142. +
  143. +       fadt->x_pm1b_cnt_blk.space_id = 1;
  144. +       fadt->x_pm1b_cnt_blk.bit_width = fadt->pm1_cnt_len * 8;
  145. +       fadt->x_pm1b_cnt_blk.bit_offset = 0;
  146. +       fadt->x_pm1b_cnt_blk.resv = 0;
  147. +       fadt->x_pm1b_cnt_blk.addrl = fadt->pm1b_cnt_blk;
  148. +       fadt->x_pm1b_cnt_blk.addrh = 0x0;
  149. +
  150. +       fadt->x_pm2_cnt_blk.space_id = 1;
  151. +       fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8;
  152. +       fadt->x_pm2_cnt_blk.bit_offset = 0;
  153. +       fadt->x_pm2_cnt_blk.resv = 0;
  154. +       fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk;
  155. +       fadt->x_pm2_cnt_blk.addrh = 0x0;
  156. +
  157. +       fadt->x_pm_tmr_blk.space_id = 1;
  158. +       fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;
  159. +       fadt->x_pm_tmr_blk.bit_offset = 0;
  160. +       fadt->x_pm_tmr_blk.resv = 0;
  161. +       fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk;
  162. +       fadt->x_pm_tmr_blk.addrh = 0x0;
  163. +
  164. +       fadt->x_gpe0_blk.space_id = 1;
  165. +       fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8;
  166. +       fadt->x_gpe0_blk.bit_offset = 0;
  167. +       fadt->x_gpe0_blk.resv = 0;
  168. +       fadt->x_gpe0_blk.addrl = fadt->gpe0_blk;
  169. +       fadt->x_gpe0_blk.addrh = 0x0;
  170. +
  171. +       fadt->x_gpe1_blk.space_id = 1;
  172. +       fadt->x_gpe1_blk.bit_width = fadt->gpe1_blk_len * 8;;
  173. +       fadt->x_gpe1_blk.bit_offset = 0;
  174. +       fadt->x_gpe1_blk.resv = 0;
  175. +       fadt->x_gpe1_blk.addrl = fadt->gpe1_blk;
  176. +       fadt->x_gpe1_blk.addrh = 0x0;
  177. +
  178. +       header->checksum = acpi_checksum((void *) fadt, sizeof(acpi_fadt_t));
  179. +}
  180. Index: src/southbridge/intel/i82371eb/Makefile.inc
  181. ===================================================================
  182. --- src/southbridge/intel/i82371eb/Makefile.inc (revision 5402)
  183. +++ src/southbridge/intel/i82371eb/Makefile.inc (working copy)
  184. @@ -26,3 +26,4 @@
  185.  driver-y +=  i82371eb_reset.o
  186.  
  187.  #initobj-y += i82371eb_early_rom.o
  188. +obj-$(CONFIG_HAVE_ACPI_TABLES) += i82371eb_fadt.o
  189. Index: src/mainboard/asus/p2b/Kconfig
  190. ===================================================================
  191. --- src/mainboard/asus/p2b/Kconfig      (revision 5402)
  192. +++ src/mainboard/asus/p2b/Kconfig      (working copy)
  193. @@ -27,6 +27,7 @@
  194.         select SUPERIO_WINBOND_W83977TF
  195.         select ROMCC
  196.         select HAVE_PIRQ_TABLE
  197. +       select HAVE_ACPI_TABLES
  198.         select UDELAY_TSC
  199.         select BOARD_ROMSIZE_KB_256
  200.  
  201. Index: src/mainboard/asus/p2b/devicetree.cb
  202. ===================================================================
  203. --- src/mainboard/asus/p2b/devicetree.cb        (revision 5402)
  204. +++ src/mainboard/asus/p2b/devicetree.cb        (working copy)
  205. @@ -50,10 +50,10 @@
  206.        register "ide1_enable" = "1"
  207.        register "ide_legacy_enable" = "1"
  208.        # Enable UDMA/33 for higher speed if your IDE device(s) support it.
  209. -      register "ide0_drive0_udma33_enable" = "0"
  210. -      register "ide0_drive1_udma33_enable" = "0"
  211. -      register "ide1_drive0_udma33_enable" = "0"
  212. -      register "ide1_drive1_udma33_enable" = "0"
  213. +      register "ide0_drive0_udma33_enable" = "1"
  214. +      register "ide0_drive1_udma33_enable" = "1"
  215. +      register "ide1_drive0_udma33_enable" = "1"
  216. +      register "ide1_drive1_udma33_enable" = "1"
  217.      end
  218.    end
  219.  end
  220. Index: src/mainboard/asus/p2b/romstage.c
  221. ===================================================================
  222. --- src/mainboard/asus/p2b/romstage.c   (revision 5402)
  223. +++ src/mainboard/asus/p2b/romstage.c   (working copy)
  224. @@ -62,10 +62,12 @@
  225.         i82371eb_enable_rom(PCI_DEV(0, 4, 0)); /* ISA bridge at 00:04.0. */
  226.  
  227.         enable_smbus();
  228. -       /* dump_spd_registers(); */
  229. +       dump_spd_registers();
  230.         sdram_set_registers();
  231.         sdram_set_spd_registers();
  232.         sdram_enable();
  233. -       /* ram_check(0, 640 * 1024); */
  234. +       ram_check(0, 640 * 1024);
  235. +       //ram_check(64 * 1024 * 1024, 640 + (64 * 1024 * 1024));
  236. +       //ram_check(256 * 1024 *1024, 640 + (256 * 1024 * 1024));
  237.  }
  238.  
  239. Index: src/mainboard/asus/p2b/acpi_tables.c
  240. ===================================================================
  241. --- src/mainboard/asus/p2b/acpi_tables.c        (revision 0)
  242. +++ src/mainboard/asus/p2b/acpi_tables.c        (revision 0)
  243. @@ -0,0 +1,176 @@
  244. +// copied from src/mainboard/asus/a8v-e_se/acpi_tables.c
  245. +
  246. +/*
  247. + * This file is part of the coreboot project.
  248. + *
  249. + * Written by Stefan Reinauer <stepan@openbios.org>.
  250. + * ACPI FADT, FACS, and DSDT table support added by
  251. + *
  252. + * Copyright (C) 2004 Stefan Reinauer <stepan@openbios.org>
  253. + * Copyright (C) 2005 Nick Barker <nick.barker9@btinternet.com>
  254. + * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
  255. + *
  256. + * This program is free software; you can redistribute it and/or modify
  257. + * it under the terms of the GNU General Public License as published by
  258. + * the Free Software Foundation; version 2 of the License.
  259. + *
  260. + * This program is distributed in the hope that it will be useful,
  261. + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  262. + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  263. + * GNU General Public License for more details.
  264. + *
  265. + * You should have received a copy of the GNU General Public License
  266. + * along with this program; if not, write to the Free Software
  267. + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  268. + */
  269. +
  270. +#include <console/console.h>
  271. +#include <string.h>
  272. +#include <arch/acpi.h>
  273. +#include <arch/smp/mpspec.h>
  274. +#include <device/device.h>
  275. +#include <device/pci_ids.h>
  276. +//#include <../../../southbridge/via/vt8237r/vt8237r.h>
  277. +//#include <../../../southbridge/via/k8t890/k8t890.h>
  278. +
  279. +extern const unsigned char AmlCode[];
  280. +
  281. +unsigned long acpi_fill_slit(unsigned long current)
  282. +{
  283. +       // Not implemented
  284. +       return current;
  285. +}
  286. +
  287. +unsigned long acpi_fill_srat(unsigned long current)
  288. +{
  289. +       // Not implemented
  290. +       return current;
  291. +}
  292. +
  293. +unsigned long acpi_fill_fadt(unsigned long current)
  294. +{
  295. +       // Not implemented
  296. +       return current;
  297. +}
  298. +
  299. +unsigned long acpi_fill_mcfg(unsigned long current)
  300. +{
  301. +//     device_t dev;
  302. +//     struct resource *res;
  303. +//
  304. +//     dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8T890CE_5, 0);
  305. +//     dev = dev_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_SMB_ACPI, 0); // pci_ids.h
  306. +//     if (!dev)
  307. +//             return current;
  308. +//
  309. +//     res = find_resource(dev, K8T890_MMCONFIG_MBAR);
  310. +//     if (res) {
  311. +//             current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)
  312. +//                             current, res->base, 0x0, 0x0, 0xff);
  313. +//     }
  314. +       return current;
  315. +}
  316. +
  317. +unsigned long acpi_fill_madt(unsigned long current)
  318. +{
  319. +//     unsigned int gsi_base = 0x18;
  320. +//
  321. +       /* Create all subtables for processors. */
  322. +//     current = acpi_create_madt_lapics(current);
  323. +//
  324. +       /* Write SB IOAPIC. */
  325. +//     current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
  326. +//                             VT8237R_APIC_ID, VT8237R_APIC_BASE, 0);
  327. +//
  328. +       /* Write NB IOAPIC. */
  329. +//     current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
  330. +//                             K8T890_APIC_ID, K8T890_APIC_BASE, gsi_base);
  331. +//
  332. +       /* IRQ9 ACPI active low. */
  333. +//     current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
  334. +//             current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW);
  335. +//
  336. +       /* IRQ0 -> APIC IRQ2. */
  337. +//     current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
  338. +//                                             current, 0, 0, 2, 0x0);
  339. +//
  340. +       /* Create all subtables for processors. */
  341. +//     current = acpi_create_madt_lapic_nmis(current,
  342. +//                     MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 1);
  343. +//
  344. +       return current;
  345. +}
  346. +
  347. +unsigned long write_acpi_tables(unsigned long start)
  348. +{
  349. +       unsigned long current;
  350. +       acpi_rsdp_t *rsdp;
  351. +       acpi_srat_t *srat;
  352. +       acpi_rsdt_t *rsdt;
  353. +       acpi_madt_t *madt;
  354. +       acpi_mcfg_t *mcfg;
  355. +       acpi_fadt_t *fadt;
  356. +       acpi_facs_t *facs;
  357. +       acpi_header_t *dsdt;
  358. +
  359. +       /* Align ACPI tables to 16 byte. */
  360. +       start = (start + 0x0f) & -0x10;
  361. +       current = start;
  362. +
  363. +       printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);
  364. +
  365. +       /* We need at least an RSDP and an RSDT table. */
  366. +       rsdp = (acpi_rsdp_t *) current;
  367. +       current += sizeof(acpi_rsdp_t);
  368. +       rsdt = (acpi_rsdt_t *) current;
  369. +       current += sizeof(acpi_rsdt_t);
  370. +
  371. +       /* Clear all table memory. */
  372. +       memset((void *) start, 0, current - start);
  373. +
  374. +       acpi_write_rsdp(rsdp, rsdt, NULL);
  375. +       acpi_write_rsdt(rsdt);
  376. +
  377. +       /* We explicitly add these tables later on: */
  378. +       printk(BIOS_DEBUG, "ACPI:     * FACS\n");
  379. +       facs = (acpi_facs_t *) current;
  380. +       current += sizeof(acpi_facs_t);
  381. +       acpi_create_facs(facs);
  382. +
  383. +       dsdt = (acpi_header_t *)current;
  384. +       memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
  385. +       current += dsdt->length;
  386. +       memcpy(dsdt, &AmlCode, dsdt->length);
  387. +       dsdt->checksum = 0;     /* Don't trust iasl to get this right. */
  388. +       dsdt->checksum = acpi_checksum((u8*)dsdt, dsdt->length);
  389. +       printk(BIOS_DEBUG, "ACPI:     * DSDT @ %p Length %x\n", dsdt,
  390. +                    dsdt->length);
  391. +       printk(BIOS_DEBUG, "ACPI:     * FADT\n");
  392. +
  393. +       fadt = (acpi_fadt_t *) current;
  394. +       current += sizeof(acpi_fadt_t);
  395. +
  396. +       acpi_create_fadt(fadt, facs, dsdt);
  397. +       acpi_add_table(rsdp, fadt);
  398. +
  399. +       /* If we want to use HPET timers Linux wants it in MADT. */
  400. +       printk(BIOS_DEBUG, "ACPI:    * MADT\n");
  401. +       madt = (acpi_madt_t *) current;
  402. +       acpi_create_madt(madt);
  403. +       current += madt->header.length;
  404. +       acpi_add_table(rsdp, madt);
  405. +       printk(BIOS_DEBUG, "ACPI:    * MCFG\n");
  406. +       mcfg = (acpi_mcfg_t *) current;
  407. +       acpi_create_mcfg(mcfg);
  408. +       current += mcfg->header.length;
  409. +       acpi_add_table(rsdp, mcfg);
  410. +
  411. +       printk(BIOS_DEBUG, "ACPI:    * SRAT\n");
  412. +       srat = (acpi_srat_t *) current;
  413. +       acpi_create_srat(srat);
  414. +       current += srat->header.length;
  415. +       acpi_add_table(rsdp, srat);
  416. +
  417. +       printk(BIOS_INFO, "ACPI: done.\n");
  418. +       return current;
  419. +}
  420. Index: src/mainboard/asus/p2b/dsdt.asl
  421. ===================================================================
  422. --- src/mainboard/asus/p2b/dsdt.asl     (revision 0)
  423. +++ src/mainboard/asus/p2b/dsdt.asl     (revision 0)
  424. @@ -0,0 +1,211 @@
  425. +/*
  426. + * This file is part of the coreboot project.
  427. + *
  428. + * Copyright (C) 2004 Nick Barker <Nick.Barker9@btinternet.com>
  429. + * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
  430. + *
  431. + * This program is free software; you can redistribute it and/or modify
  432. + * it under the terms of the GNU General Public License as published by
  433. + * the Free Software Foundation; version 2 of the License.
  434. + *
  435. + * This program is distributed in the hope that it will be useful,
  436. + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  437. + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  438. + * GNU General Public License for more details.
  439. + *
  440. + * You should have received a copy of the GNU General Public License
  441. + * along with this program; if not, write to the Free Software
  442. + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  443. + */
  444. +
  445. +/*
  446. + * ISA portions taken from QEMU acpi-dsdt.dsl.
  447. + */
  448. +
  449. +DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1)
  450. +{
  451. +       /* Define the main processor.*/
  452. +       Scope (\_PR)
  453. +       {
  454. +               Processor (\_PR.CPU0, 0x00, 0x000000, 0x00) {}
  455. +               Processor (\_PR.CPU1, 0x01, 0x000000, 0x00) {}
  456. +       }
  457. +
  458. +       /* For now only define 2 power states:
  459. +        *  - S0 which is fully on
  460. +        *  - S5 which is soft off
  461. +        * Any others would involve declaring the wake up methods.
  462. +        */
  463. +       Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 })
  464. +       Name (\_S5, Package () { 0x02, 0x02, 0x00, 0x00 })
  465. +
  466. +       /* Root of the bus hierarchy */
  467. +       Scope (\_SB)
  468. +       {
  469. +               /* Top PCI device */
  470. +               Device (PCI0)
  471. +               {
  472. +                       Name (_HID, EisaId ("PNP0A03"))
  473. +                       Name (_ADR, 0x00)
  474. +                       Name (_UID, 0x00)
  475. +                       Name (_BBN, 0x00)
  476. +
  477. +                       /* PCI Routing Table */
  478. +                       /* aaa */
  479. +                       Name (_PRT, Package () {
  480. +                               Package (0x04) { 0x000BFFFF, 0x00, 0x00, 0x10 }, /* Slot 0xB */
  481. +                               Package (0x04) { 0x000BFFFF, 0x01, 0x00, 0x11 },
  482. +                               Package (0x04) { 0x000BFFFF, 0x02, 0x00, 0x12 },
  483. +                               Package (0x04) { 0x000BFFFF, 0x03, 0x00, 0x13 },
  484. +                               Package (0x04) { 0x000CFFFF, 0x00, 0x00, 0x11 }, /* Slot 0xC */
  485. +                               Package (0x04) { 0x000CFFFF, 0x01, 0x00, 0x12 },
  486. +                               Package (0x04) { 0x000CFFFF, 0x02, 0x00, 0x13 },
  487. +                               Package (0x04) { 0x000CFFFF, 0x03, 0x00, 0x10 },
  488. +                               Package (0x04) { 0x000DFFFF, 0x00, 0x00, 0x12 }, /* Slot 0xD */
  489. +                               Package (0x04) { 0x000DFFFF, 0x01, 0x00, 0x13 },
  490. +                               Package (0x04) { 0x000DFFFF, 0x02, 0x00, 0x10 },
  491. +                               Package (0x04) { 0x000DFFFF, 0x03, 0x00, 0x11 },
  492. +                               Package (0x04) { 0x000FFFFF, 0x01, 0x00, 0x14 }, /* 0xf SATA IRQ 20 */
  493. +                               Package (0x04) { 0x000FFFFF, 0x00, 0x00, 0x14 }, /* 0xf Native IDE IRQ 20 */
  494. +                               Package (0x04) { 0x0010FFFF, 0x00, 0x00, 0x15 }, /* USB routing */
  495. +                               Package (0x04) { 0x0010FFFF, 0x01, 0x00, 0x15 },
  496. +                               Package (0x04) { 0x0010FFFF, 0x02, 0x00, 0x15 },
  497. +                               Package (0x04) { 0x0010FFFF, 0x03, 0x00, 0x15 },
  498. +                               Package (0x04) { 0x0011FFFF, 0x02, 0x00, 0x16 }, /* AC97, MC97 */
  499. +                               Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1B }, /* PCIE16 bridge IRQ27 */
  500. +                               Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1B },
  501. +                               Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x1B },
  502. +                               Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x1B },
  503. +                               Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1F }, /* PCIE bridge IRQ31 */
  504. +                               Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x23 }, /* IRQ36 */
  505. +                               Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x27 }, /* IRQ39 */
  506. +                               Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x2B }  /* IRQ43 */
  507. +                       })
  508. +
  509. +                       Device (PEGG)
  510. +                       {
  511. +                               Name (_ADR, 0x00020000)
  512. +                               Name (_UID, 0x00)
  513. +                               Name (_BBN, 0x02)
  514. +                               Name (_PRT, Package () {
  515. +                                       Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x18 }, /* PCIE IRQ24-IRQ27 */
  516. +                                       Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x19 },
  517. +                                       Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1A },
  518. +                                       Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1B },
  519. +                               })
  520. +                       }
  521. +
  522. +                       Device (PEX0)
  523. +                       {
  524. +                               Name (_ADR, 0x00030000)
  525. +                               Name (_UID, 0x00)
  526. +                               Name (_BBN, 0x03)
  527. +                               Name (_PRT, Package () {
  528. +                                       Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x1C }, /* PCIE IRQ28-IRQ31 */
  529. +                                       Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x1D },
  530. +                                       Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1E },
  531. +                                       Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1F },
  532. +                               })
  533. +                       }
  534. +
  535. +                       Device (PEX1)
  536. +                       {
  537. +                               Name (_ADR, 0x00030001)
  538. +                               Name (_UID, 0x00)
  539. +                               Name (_BBN, 0x04)
  540. +                               Name (_PRT, Package () {
  541. +                                       Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x20 }, /* PCIE IRQ32-IRQ35 */
  542. +                                       Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x21 },
  543. +                                       Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x22 },
  544. +                                       Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x23 },
  545. +                               })
  546. +                       }
  547. +
  548. +                       Device (PEX2)
  549. +                       {
  550. +                               Name (_ADR, 0x00030002)
  551. +                               Name (_UID, 0x00)
  552. +                               Name (_BBN, 0x05)
  553. +                               Name (_PRT, Package () {
  554. +                                       Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x24 }, /* PCIE IRQ36-IRQ39 */
  555. +                                       Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x25 },
  556. +                                       Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x26 },
  557. +                                       Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x27 },
  558. +                               })
  559. +                       }
  560. +
  561. +                       Device (PEX3)
  562. +                       {
  563. +                               Name (_ADR, 0x00030003)
  564. +                               Name (_UID, 0x00)
  565. +                               Name (_BBN, 0x06)
  566. +                               Name (_PRT, Package () {
  567. +                                       Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x28 }, /* PCIE IRQ40-IRQ43 */
  568. +                                       Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x29 },
  569. +                                       Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x2A },
  570. +                                       Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x2B },
  571. +                               })
  572. +                       }
  573. +
  574. +                       Device (ISA) {
  575. +                               Name (_ADR, 0x00110000)
  576. +
  577. +                               /* PS/2 keyboard (seems to be important for WinXP install) */
  578. +                               Device (KBD)
  579. +                               {
  580. +                                       Name (_HID, EisaId ("PNP0303"))
  581. +                                       Method (_STA, 0, NotSerialized)
  582. +                                       {
  583. +                                               Return (0x0f)
  584. +                                       }
  585. +                                       Method (_CRS, 0, NotSerialized)
  586. +                                       {
  587. +                                               Name (TMP, ResourceTemplate () {
  588. +                                                       IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
  589. +                                                       IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
  590. +                                                       IRQNoFlags () {1}
  591. +                                               })
  592. +                                               Return (TMP)
  593. +                                       }
  594. +                               }
  595. +
  596. +                               /* PS/2 mouse */
  597. +                               Device (MOU)
  598. +                               {
  599. +                                       Name (_HID, EisaId ("PNP0F13"))
  600. +                                       Method (_STA, 0, NotSerialized)
  601. +                                       {
  602. +                                               Return (0x0f)
  603. +                                       }
  604. +                                       Method (_CRS, 0, NotSerialized)
  605. +                                       {
  606. +                                               Name (TMP, ResourceTemplate () {
  607. +                                                    IRQNoFlags () {12}
  608. +                                               })
  609. +                                               Return (TMP)
  610. +                                       }
  611. +                               }
  612. +
  613. +                               /* PS/2 floppy controller */
  614. +                               Device (FDC0)
  615. +                               {
  616. +                                       Name (_HID, EisaId ("PNP0700"))
  617. +                                       Method (_STA, 0, NotSerialized)
  618. +                                       {
  619. +                                               Return (0x0f)
  620. +                                       }
  621. +                                       Method (_CRS, 0, NotSerialized)
  622. +                                       {
  623. +                                               Name (BUF0, ResourceTemplate () {
  624. +                                                       IO (Decode16, 0x03F2, 0x03F2, 0x00, 0x04)
  625. +                                                       IO (Decode16, 0x03F7, 0x03F7, 0x00, 0x01)
  626. +                                                       IRQNoFlags () {6}
  627. +                                                       DMA (Compatibility, NotBusMaster, Transfer8) {2}
  628. +                                               })
  629. +                                               Return (BUF0)
  630. +                                       }
  631. +                               }
  632. +                       }
  633. +               }
  634. +       }
  635. +}
  636. Index: src/northbridge/intel/i440bx/raminit.c
  637. ===================================================================
  638. --- src/northbridge/intel/i440bx/raminit.c      (revision 5402)
  639. +++ src/northbridge/intel/i440bx/raminit.c      (working copy)
  640. @@ -925,7 +925,7 @@
  641.         set_dram_row_attributes();
  642.  
  643.         /* TODO: Set SDRAMC. */
  644. -       pci_write_config16(NB, SDRAMC, 0x0010); /* SDRAMPWR=1: 4 DIMM config */
  645. +       pci_write_config16(NB, SDRAMC, 0x0000); /* SDRAMPWR=0: 3 DIMM config */
  646.  
  647.         /* TODO */
  648.         set_dram_buffer_strength();
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