antras komp architektura

--pasikeisti skiltis
--Operacinio itaiso (priverstinei adresacijai)
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

entity operacinis is
port (  Y   :   in  std_logic_vector(1 to 17);
    clock   :   in  std_logic;
    reset   :   in  std_logic;
       X    :   out std_logic_vector(1 to 2);
     Duom   :   in  std_logic_vector( 7 downto 0) := "00000000";
      Rez   :   out std_logic_vector(14 downto 0)
      );
end operacinis;
-----------------------------------------------------
architecture ALU of operacinis is

begin
    process (reset,clock)
        variable A : std_logic_vector(14 downto 0);
        variable L : std_logic_vector(6 downto 0);
        variable M : std_logic_vector(6 downto 0);
        variable B : std_logic_vector( 7 downto 0);
        variable C : std_logic_vector(14 downto 0);
        variable Sk: integer range 0 to 7;
    begin
        if reset= '1' then
           C  := "000000000000000";  -- clear sandauga
           A  := "000000000000000";  -- clear A
           L  := "0000000";
           M  := "0000000";
           B  := "00000000";       -- clear B
           X  <= "00";             -- clear LS
      elsif clock'event and clock = '1' then
        ------------------------------------------------------------

        if    Y(1) = '1' then
            A(7 downto 0)  := Duom;   --  load  A
            A(14 downto 7) := "00000000";--"11111111"; -- uzpildo kaire puse
        end if;
        ---------------------------------------------
        if    Y(2) = '1' then
            B  := Duom;   --  load  B
            --X(1) <= B(7);
            C  := "000000000000000";  -- clear C
            Sk  := 7;   --  load  Sk
        end if;
        ---------------------------------------------


        ---------------------------------------------
        if    Y(3) = '1' then
            L := A(6 downto 0);
        end if;
        ---------------------------------------------
        if    Y(4) = '1' then
            M(6 downto 0) := not L + 1;
        end if;
        ---------------------------------------------
        if    Y(5) = '1' then
            A(6 downto 0) := M;
        end if;
        ---------------------------------------------


        ---------------------------------------------
        if    Y(6) = '1' then
            X(1) <= B(7); -- ar auksciausia skiltis = 1, jei taip, darom adresas + 1
        end if;
        ---------------------------------------------
        if    Y(7) = '1' then
            C  := C + A;
        end if;
        ---------------------------------------------
        if    Y(8) = '1' then
             B  := B(6 downto 0) & '0';   --  shift  B to left
             C  := C(13 downto 0) & '0';  --  shift  C to left
             --X(1) <= B(7); -- jei B(7) = 1, tai X(1) = 1
        end if;
        ---------------------------------------------
        if    Y(9) = '1' then
            if Sk > 0 then
                Sk  := Sk - 1;   --  decrement Sk
                X(2) <= '1';
            else
                X(2) <= '0';
            end if;
        end if;
        ---------------------------------------------


        ---------------------------------------------
        if    Y(16) = '1' then
            C := '0' & C(14 downto 1);   -- Grazina C vienu atgal
            Rez <= C;
        end if;
        ---------------------------------------------
        if    Y(17) = '1' then
            assert 1 = 0 report "Modeliavimas baigtas" severity failure;
        end if;

        ------------------------------------------------------------
  end if;
end process;
end ALU;

-- ALU

--////////////////////////////////////////////////////////////////////////////////////////////////////
--Mikroprograminio valdymo itaiso komponentai----------------------------------------------------------------------------------------------------------------------
    -- id1
    --mikrokomandu atmint? MK_ROM,
    --i? kurios pagal suformuot? paskesn?s MK adres? (Next_MK) i?renkama mikrokomanda (Mikrokom);

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity MK_ROM is
port( Clock : in  std_logic;
    next_MK : in  std_logic_vector(0 to 3);
   Mikrokom : out std_logic_vector(1 to 23)
    );
end MK_ROM;
--------------------------------------------------------
architecture MK_Atmintis of MK_ROM is

    type MK_Array is array (0 to 30) of std_logic_vector(1 to 23);

    constant Content: MK_Array := (
        -- X(1) = 01 , X(2) = 10
        -- paskutiniai 4 rodo i kur (priekinis adresas nurodo i kur)
    -- ADR
        0 => "10000000000000000000001", --Y(1)
        1 => "01000000000000000000011", --Y(2) atjungtas 2 adresas, keliauja i 3 iskart

        --2 => "00111000000000000000011", -- Y(3), Y(4), Y(5) | A pavertimas i papildoma koda

        3 => "00000100000000000010100", -- Y(6) tikrina pirma reiksme, jeigu = 1, tai persokam i sudeti /// jeigu noredemi, kad keliautu i 100, keliaus tada i 101
        4 => "00000001000000000000110", -- Y(8) postumis
        5 => "00000010000000000000100", -- Y(7) sudetis, butinai turi pereiti i 4 vel i postumi
        6 => "00000000100000000100111", -- Y(9) sk - 1 ir X(2)
        7 => "00000000000000010001001", -- Y(16)rez = c
        8 => "00000000000000000000011", -- ciiiiiiiiiiiiiiiiiklas, kai sk <> 0, griztam i 3 adresa
        9 => "00000000000000001001001", -- Y(17) stabdo viska

        10 => "00000000000000000000000",
       11 => "00000000000000000000000",
       12 => "00000000000000000000000",
       13 => "00000000000000000000000",

        --8 => "0000000010001010", --Y(9)
        --9 => "0000000001001010", --Y(10)

--ciklas be sudeties
--5 => "0000001000000111", --Y(6)  postumiai
--6 => "0000010000000110", --Y(7)  sudetis
--7 => "0000000100100100", --Y(8)  sk - 1
   OTHERS => "00000000000000000000000"
);

begin MK_skaitymas:
    process (Clock, next_MK)
    begin
       if ( Clock'event and Clock = '1' ) then
      Mikrokom <= Content(conv_integer(next_MK));
       end if;
    end process;
end MK_Atmintis;

--////////////////////////////////////////////////////////////////////////////////////////////////////
    -- id2
    --mikrokomandu skirstymo schem? MK_Form,
    --kurioje nauja mikrokomanda (Mikrokom) padalijama ? tris laukus - mikrooperaciju lauk? (Y),
    --login?s s?lygos numerio lauk? (LS) ir adreso lauk? (Addr), skirt? paskesn?s MK adresui formuoti;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

Entity MK_Form is
port (
   Mikrokom : in  std_logic_vector(1 to 23);
    Y   : out std_logic_vector(1 to 17);
    LS  : out std_logic_vector(0 to 1);
    Addr    : out std_logic_vector(0 to 3)
       );
end  MK_Form;
-------------------------------------------------------------
architecture Skirstymas of  MK_Form is
begin
       Y    <= Mikrokom(1 to 17);
       LS   <= Mikrokom(18 to 19);
       Addr <= Mikrokom(20 to 23);
end Skirstymas;

--////////////////////////////////////////////////////////////////////////////////////////////////////
    -- id3
    --paskesn?s mikrokomandos adreso formavimo schem? MK_AR_Form,
    --kuri pagal mikrokomandoje esan?i? informacij? (LS, Addr) ir (jei to reikia) tikrinamos
    --login?s s?lygos (LS_Values) reik?me formuoja paskesn?s MK adres? (next_MKAdr);

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

Entity MK_AR_Form is
port(    LS : in  std_logic_vector(0 to 1);
   LS_values    : in  std_logic_vector(1 to 2);
        Addr    : in  std_logic_vector(0 to 3);
    next_Adr    : out std_logic_vector(0 to 3);
       clock    : in  std_logic
    );
end  MK_AR_Form;
---------------------------------------------------------
architecture Behav of  MK_AR_Form is

begin process (clock)
   variable xx : integer;
begin
     xx := conv_integer(LS);
     if (clock'event and clock='1') then
     if (xx = 0) then
           next_Adr <= Addr;
     elsif (LS_values(xx)='0') then
           next_Adr <= Addr;
     elsif (LS_values(xx)='1') then
           next_Adr <= Addr +'1';
     end if;
     end if;
   end process;
end Behav;

--////////////////////////////////////////////////////////////////////////////////////////////////////
    -- id4
    --mikrokomandos adreso registr? MK_AR, kuriame saugomas i?renkamos mikrokomandos adresas (MK_Addr).

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

Entity MK_AR is
port (  Clock : in  std_logic;
        Reset : in  std_logic;
   next_MKAdr : in  std_logic_vector(0 to 3);
      MK_Addr : out std_logic_vector(0 to 3)
);
end MK_AR;
------------------------------------------------------------
architecture Behav of MK_AR is
 begin
 process (Reset, clock)
   begin
       if (Reset = '1') then
          MK_Addr <= "0000";
       elsif (clock'event and clock='1') then
             MK_Addr <= next_MKAdr;
       end if;
   end process;
end Behav;


--////////////////////////////////////////////////////////////////////////////////////////////////////
--Mikroprograminio valdymo komponentu apjungimas----------------------------------------------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity ProgLog_top is
    port(
     sinchr1 : in std_logic;
     sinchr2 : in std_logic;
     sinchr3 : in std_logic;
     sinchr4 : in std_logic;
     prad    : in std_logic;
        Data : in  std_logic_vector( 7 downto 0);  -- operandai
        Res  : out std_logic_vector(14 downto 0)   -- sandauga
     );
end ProgLog_top;

architecture struktura of ProgLog_top is
-------------------------------------------
--- komponentai                          ---
-------------------------------------------
component MK_ROM is
port(  Clock: in std_logic;
    next_MK : in std_logic_vector(0 to 3);
    Mikrokom: out std_logic_vector(1 to 23)
    );
end component;

component MK_AR is
port(   Clock : in std_logic;
        Reset : in std_logic;
   next_MKAdr : in std_logic_vector(0 to 3);
      MK_Addr : out std_logic_vector(0 to 3)
);
end component;

component MK_AR_Form is
port(   LS  : in  std_logic_vector(0 to 1);
  LS_values : in  std_logic_vector(1 to 2);
      Addr  : in  std_logic_vector(0 to 3);
   next_Adr : out std_logic_vector(0 to 3);
      clock : in  std_logic
);
end component;

component MK_Form is
port(
    Mikrokom: in  std_logic_vector(1 to 23);
       Y    : out std_logic_vector(1 to 17);
       LS   : out std_logic_vector(0 to 1);
       Addr : out std_logic_vector(0 to 3)
);
end component;

component operacinis is
port(   Y   : in std_logic_vector(1 to 17);
    clock   :   in  std_logic;
    reset   :   in  std_logic;
        X   :   out std_logic_vector(1 to 2);
    Duom    :   in  std_logic_vector( 7 downto 0) := "00000000";
      Rez   :   out std_logic_vector(14 downto 0)
  );
end component;


-------------------------------------------
--- Sujungimams                         ---
-------------------------------------------
signal logsnr   :   std_logic_vector(0 to 1);  -- log. sal. nr.
signal log_sal  :   std_logic_vector(1 to 2);  -- logines salygos
signal mops     :   std_logic_vector(1 to 17); -- mikrooperacijos
signal mk       :   std_logic_vector(1 to 23); -- mikrokomanda
signal mkad1    :   std_logic_vector(0 to 3);  -- MK adresas
signal mkad2    :   std_logic_vector(0 to 3);  -- MK adresas
signal mkad3    :   std_logic_vector(0 to 3);  -- MK adresas

begin

ALU1: operacinis port map (
    Y       => mops,
    clock => sinchr3,
    reset => prad,
    X     => log_sal,
    Duom  => Data,
    Rez   => Res
   );

Vald1: MK_ROM port map(
      Clock => sinchr2,
    next_MK => mkad1,
    Mikrokom => mk
    );

Vald2: MK_AR port map(
      Clock => sinchr1,
      Reset => prad,
    next_MKAdr=> mkad3,
    MK_Addr => mkad1
    );

Vald3: MK_AR_Form port map (
    LS  => logsnr,
    LS_values=> log_sal,
    Addr    => mkad2,
    next_Adr    => mkad3,
    clock   => sinchr4
);

  Vald4: MK_Form port map (
    Mikrokom    => mk,
    Y       => mops,
    LS  => logsnr,
    Addr    => mkad2
);
end struktura;


--      0 => "1000000000000001", --Y(1) --> Y(2)
--      1 => "0100000000010101", --Y(2) --> Y(3)
--      --1 => "0100000000010010", --Y(2) --> Y(3)
--
--      --2 => "0010000000000011", --Y(3) --> Y(4)
--      --3 => "0001000000000100", --Y(4) --> Y(5)
--      --4 => "0000100000000101", --Y(5) --> Y(6)
--
--      5 => "0000001000000110", --Y(6) --> Y(7) sudetis
--      6 => "0000010000000111", --Y(7) --> Y(8) postumis
--      7 => "0000000100100100", --Y(8) --> Y(6) sk - 1
--
--      --8 => "0000000010001010", --Y(9)
--      --9 => "0000000001001010", --Y(10)