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| 1 | module Lab5( | |
| 2 | input CLOCK_50, | |
| 3 | input [3:0] KEY, | |
| 4 | - | output reg [1:0] LEDR, |
| 4 | + | output reg [17:0] LEDR, |
| 5 | - | inout [35:0] GPIO_0, |
| 5 | + | inout reg [35:0] GPIO_0, |
| 6 | output reg [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7 | |
| 7 | ); | |
| 8 | ||
| 9 | - | reg [31:0] time4k, time50, count; |
| 9 | + | reg [31:0] time4k, time50, time118; |
| 10 | - | reg flag; |
| 10 | + | reg [15:0] count, index, sum, duty; |
| 11 | - | wire [6:0] h0,h1,h2,h3,h4,h5,h6,h7; |
| 11 | + | reg [15:0] freq[0:2],temp[0:2]; |
| 12 | reg [7:0] div, setTemp, avTemp; | |
| 13 | - | hex_7seg(count%10, h0); |
| 13 | + | reg flag1, flag2; |
| 14 | - | hex_7seg(count/10%10, h1); |
| 14 | + | wire [6:0] h0,h1,h2,h3,h4,h5,h6,h7,s0,s1; |
| 15 | - | hex_7seg(count/100%10, h2); |
| 15 | + | wire K0, K1, K2, K3; |
| 16 | - | hex_7seg(count/1000%10, h3); |
| 16 | + | |
| 17 | hex_7seg(count%10, h0); | |
| 18 | hex_7seg(count/10%10, h1); | |
| 19 | hex_7seg(count/100%10, h2); | |
| 20 | hex_7seg(count/1000%10, h3); | |
| 21 | ||
| 22 | - | always @(posedge CLOCK_50) begin |
| 22 | + | hex_7seg(setTemp%10,h4); |
| 23 | hex_7seg(setTemp/10%10,h5); | |
| 24 | ||
| 25 | - | if(time4k >=4000) begin |
| 25 | + | hex_7seg(((temp[0]+temp[1]+temp[2])/3)%10, h6); |
| 26 | hex_7seg(((temp[0]+temp[1]+temp[2])/3)/10%10, h7); | |
| 27 | - | flag = 1; |
| 27 | + | |
| 28 | hex_7seg(setTemp%10,s0); | |
| 29 | - | else begin |
| 29 | + | hex_7seg(setTemp/10%10,s1); |
| 30 | - | LEDR[0] = 1'b0; |
| 30 | + | |
| 31 | - | flag = 0; |
| 31 | + | oneshot g(K1, CLOCK_50, ~KEY[1]); |
| 32 | //hex_7seg( | |
| 33 | ||
| 34 | initial begin | |
| 35 | time50 = 0; | |
| 36 | time4k = 0; | |
| 37 | time118 = 0; | |
| 38 | flag1 = 0; | |
| 39 | flag2 = 0; | |
| 40 | div = 2; | |
| 41 | setTemp = 24; | |
| 42 | - | always@(negedge GPIO_0[0] && !flag) begin |
| 42 | + | index = 0; |
| 43 | - | count <= count + 1; |
| 43 | + | duty = 423728/2; |
| 44 | end | |
| 45 | ||
| 46 | always begin | |
| 47 | if(!KEY[0]) begin | |
| 48 | LEDR[3] = 1; | |
| 49 | HEX6 <= s0; | |
| 50 | HEX7 <= s1; | |
| 51 | - | output [6:0] seg; |
| 51 | + | |
| 52 | - | reg [6:0] seg; |
| 52 | + | else begin |
| 53 | LEDR[3] = 0; | |
| 54 | HEX6 <= h6; | |
| 55 | HEX7 <= h7; | |
| 56 | end | |
| 57 | ||
| 58 | ||
| 59 | ||
| 60 | ||
| 61 | ||
| 62 | HEX0 <= h0; | |
| 63 | HEX1 <= h1; | |
| 64 | HEX2 <= h2; | |
| 65 | HEX3 <= h3; | |
| 66 | ||
| 67 | HEX4 <= h4; | |
| 68 | HEX5 <= h5; | |
| 69 | ||
| 70 | /*HEX6 <= h6; | |
| 71 | HEX7 <= h7;*/ | |
| 72 | end | |
| 73 | ||
| 74 | always @(negedge CLOCK_50) begin | |
| 75 | ||
| 76 | if(K1) begin | |
| 77 | setTemp = setTemp+1; | |
| 78 | if(setTemp > 28) | |
| 79 | setTemp = 20; | |
| 80 | end | |
| 81 | ||
| 82 | if(time50 >= 12500) begin | |
| 83 | time4k = time4k + 1; | |
| 84 | if(time4k >= 4000) begin | |
| 85 | LEDR[0] = 1'b1; | |
| 86 | flag1 = 1; | |
| 87 | time4k = 0; | |
| 88 | end | |
| 89 | if(flag2) begin | |
| 90 | flag1 = 0; | |
| 91 | end | |
| 92 | time50 = 0; | |
| 93 | end | |
| 94 | ||
| 95 | time50 = time50+1; | |
| 96 | ||
| 97 | end | |
| 98 | ||
| 99 | always @ (negedge GPIO_0[0]) begin | |
| 100 | count = count + 1; | |
| 101 | if(flag1) begin | |
| 102 | ||
| 103 | LEDR[2] = ~LEDR[2]; | |
| 104 | freq[index] = count; | |
| 105 | //freq[index] = count; | |
| 106 | ||
| 107 | temp[index] = 16 + ((((freq[index])) - 800)/110); | |
| 108 | index = index + 1; | |
| 109 | count = 0; | |
| 110 | flag2 = 1; | |
| 111 | end | |
| 112 | else begin | |
| 113 | flag2 = 0; | |
| 114 | if(index > 2) | |
| 115 | index = 0; | |
| 116 | end | |
| 117 | ||
| 118 | end | |
| 119 | ||
| 120 | always@(negedge CLOCK_50) begin | |
| 121 | ||
| 122 | if(time118 >= 423728) begin | |
| 123 | time118 = 0; | |
| 124 | end | |
| 125 | ||
| 126 | if(time118 <= 423728/2) begin | |
| 127 | LEDR[1] = 1'b1; | |
| 128 | GPIO_0[1] = 1'b1; | |
| 129 | end | |
| 130 | else begin | |
| 131 | LEDR[1] = 1'b0; | |
| 132 | GPIO_0[1] = 1'b0; | |
| 133 | end | |
| 134 | ||
| 135 | time118 = time118 + 1; | |
| 136 | end | |
| 137 | ||
| 138 | endmodule | |
| 139 | ||
| 140 | module oneshot(output reg pulse_out,input clk,input trigger_in); | |
| 141 | reg delay; | |
| 142 | ||
| 143 | always @ (posedge clk) | |
| 144 | begin | |
| 145 | if (trigger_in && !delay) pulse_out <= 1'b1; | |
| 146 | else pulse_out <= 1'b0; | |
| 147 | delay <= trigger_in; | |
| 148 | end | |
| 149 | endmodule | |
| 150 | ||
| 151 | ||
| 152 | module hex_7seg(hex_digit,seg); | |
| 153 | input [3:0] hex_digit; | |
| 154 | output reg [6:0] seg; | |
| 155 | // seg = {g,f,e,d,c,b,a};
| |
| 156 | // 0 is on and 1 is off | |
| 157 | ||
| 158 | always @ (hex_digit) | |
| 159 | case (hex_digit) | |
| 160 | 4'h0: seg = 7'b1000000; | |
| 161 | 4'h1: seg = 7'b1111001; // ---a---- | |
| 162 | 4'h2: seg = 7'b0100100; // | | | |
| 163 | 4'h3: seg = 7'b0110000; // f b | |
| 164 | 4'h4: seg = 7'b0011001; // | | | |
| 165 | 4'h5: seg = 7'b0010010; // ---g---- | |
| 166 | 4'h6: seg = 7'b0000010; // | | | |
| 167 | 4'h7: seg = 7'b1111000; // e c | |
| 168 | 4'h8: seg = 7'b0000000; // | | | |
| 169 | 4'h9: seg = 7'b0011000; // ---d---- | |
| 170 | 4'ha: seg = 7'b0001000; | |
| 171 | 4'hb: seg = 7'b0000011; | |
| 172 | 4'hc: seg = 7'b1000110; | |
| 173 | 4'hd: seg = 7'b0100001; | |
| 174 | 4'he: seg = 7'b0000110; | |
| 175 | 4'hf: seg = 7'b0001110; | |
| 176 | endcase | |
| 177 | endmodule |