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module Lab5(
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				input CLOCK_50,
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				input [3:0] KEY,
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				output reg [1:0] LEDR,
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				output reg [17:0] LEDR,
5-
				inout [35:0] GPIO_0,
5+
				inout reg [35:0] GPIO_0,
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				output reg [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7
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);
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	 reg [31:0] time4k, time50, count;
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	reg [31:0] time4k, time50, time118;
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	 reg flag;
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	reg [15:0] count, index, sum, duty;
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	 wire [6:0] h0,h1,h2,h3,h4,h5,h6,h7;
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	reg [15:0] freq[0:2],temp[0:2];
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	reg [7:0] div, setTemp, avTemp;
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    hex_7seg(count%10, h0);
13+
	reg flag1, flag2;
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	 hex_7seg(count/10%10, h1);
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	wire [6:0] h0,h1,h2,h3,h4,h5,h6,h7,s0,s1;
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	 hex_7seg(count/100%10, h2);
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	wire K0, K1, K2, K3;
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	 hex_7seg(count/1000%10, h3);
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   hex_7seg(count%10, h0);
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	hex_7seg(count/10%10, h1);
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	hex_7seg(count/100%10, h2);
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	hex_7seg(count/1000%10, h3);
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    always @(posedge CLOCK_50) begin
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	hex_7seg(setTemp%10,h4);
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	hex_7seg(setTemp/10%10,h5);
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			if(time4k >=4000) begin
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	hex_7seg(((temp[0]+temp[1]+temp[2])/3)%10, h6);
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	hex_7seg(((temp[0]+temp[1]+temp[2])/3)/10%10, h7);
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					flag = 1;
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	hex_7seg(setTemp%10,s0);
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			else begin
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	hex_7seg(setTemp/10%10,s1);
30-
				LEDR[0] = 1'b0;
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				flag = 0;
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	oneshot g(K1, CLOCK_50, ~KEY[1]);
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	 //hex_7seg(
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    initial begin
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        time50 = 0;
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		  time4k = 0;
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		  time118 = 0;
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		  flag1 = 0;
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		  flag2 = 0;
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		  div = 2;
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		  setTemp = 24;
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	 always@(negedge GPIO_0[0] && !flag) begin
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		  index = 0;
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		count <= count + 1;
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		  duty = 423728/2;
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    end
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	always begin
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		if(!KEY[0]) begin
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			LEDR[3] = 1;
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			HEX6 <= s0;
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			HEX7 <= s1;
51-
output [6:0] seg;
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reg [6:0] seg;
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		else begin
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			LEDR[3] = 0;
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			HEX6 <= h6;
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			HEX7 <= h7;
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		end
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		HEX0 <= h0;
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		HEX1 <= h1;
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		HEX2 <= h2;
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		HEX3 <= h3;
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		HEX4 <= h4;
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		HEX5 <= h5;
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		/*HEX6 <= h6;
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		HEX7 <= h7;*/
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	end
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	always @(negedge CLOCK_50) begin
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		if(K1) begin
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			setTemp = setTemp+1;
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			if(setTemp > 28)
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				setTemp = 20;
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		end
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		if(time50 >= 12500) begin
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			time4k = time4k + 1;
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			if(time4k >= 4000) begin
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					LEDR[0] = 1'b1;
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					flag1 = 1;
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					time4k = 0;
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			end
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			if(flag2) begin
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				flag1 = 0;
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			end
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			time50 = 0;
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		end
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		time50 = time50+1;
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	end
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	 always @ (negedge GPIO_0[0]) begin
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		count = count + 1;
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		if(flag1) begin
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			LEDR[2] = ~LEDR[2];
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			freq[index] = count;
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			//freq[index] = count;
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			temp[index] = 16 + ((((freq[index])) - 800)/110);
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			index = index + 1;
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			count = 0;
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			flag2 = 1;
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		end
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		else begin
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			flag2 = 0;
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			if(index > 2)
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				index = 0;
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		end
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	 end
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	always@(negedge CLOCK_50) begin
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		if(time118 >= 423728) begin
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			time118 = 0;
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		end
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		if(time118 <= 423728/2) begin
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			LEDR[1] = 1'b1;
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			GPIO_0[1] = 1'b1;
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		end
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		else begin
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			LEDR[1] = 1'b0;
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			GPIO_0[1] = 1'b0;
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		end
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		time118 = time118 + 1;
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	end
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endmodule
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module oneshot(output reg pulse_out,input clk,input trigger_in);
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reg delay;
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always @ (posedge clk)
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begin
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       if (trigger_in && !delay) pulse_out <= 1'b1;
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       else pulse_out <= 1'b0;
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               delay <= trigger_in;
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end
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endmodule
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module hex_7seg(hex_digit,seg);
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input [3:0] hex_digit;
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output reg [6:0] seg;
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// seg = {g,f,e,d,c,b,a};
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// 0 is on and 1 is off
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always @ (hex_digit)
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case (hex_digit)
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        4'h0: seg = 7'b1000000;
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        4'h1: seg = 7'b1111001;     // ---a----
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        4'h2: seg = 7'b0100100;     // |      |
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        4'h3: seg = 7'b0110000;     // f      b
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        4'h4: seg = 7'b0011001;     // |      |
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        4'h5: seg = 7'b0010010;     // ---g----
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        4'h6: seg = 7'b0000010;     // |      |
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        4'h7: seg = 7'b1111000;     // e      c
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        4'h8: seg = 7'b0000000;     // |      |
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        4'h9: seg = 7'b0011000;     // ---d----
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        4'ha: seg = 7'b0001000;
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        4'hb: seg = 7'b0000011;
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        4'hc: seg = 7'b1000110;
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        4'hd: seg = 7'b0100001;
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        4'he: seg = 7'b0000110;
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        4'hf: seg = 7'b0001110;
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endcase
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endmodule