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- module Lab5(
- input CLOCK_50,
- input [3:0] KEY,
- output reg [1:0] LEDR,
- inout [35:0] GPIO_0,
- output reg [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7
- );
- reg [31:0] time4k, time50, count;
- reg flag;
- wire [6:0] h0,h1,h2,h3,h4,h5,h6,h7;
- hex_7seg(count%10, h0);
- hex_7seg(count/10%10, h1);
- hex_7seg(count/100%10, h2);
- hex_7seg(count/1000%10, h3);
- initial begin
- time50 = 0;
- time4k = 0;
- end
- always @(posedge CLOCK_50) begin
- if(time50 >= 12500) begin
- time4k = time4k + 1;
- if(time4k >=4000) begin
- LEDR[0] = 1'b1;
- flag = 1;
- end
- else begin
- LEDR[0] = 1'b0;
- flag = 0;
- end
- time50 = 0;
- end
- time50 = time50+1;
- HEX0 <= h0;
- HEX1 <= h1;
- HEX2 <= h2;
- end
- always@(negedge GPIO_0[0] && !flag) begin
- count <= count + 1;
- end
- endmodule
- module hex_7seg(hex_digit,seg);
- input [3:0] hex_digit;
- output [6:0] seg;
- reg [6:0] seg;
- // seg = {g,f,e,d,c,b,a};
- // 0 is on and 1 is off
- always @ (hex_digit)
- case (hex_digit)
- 4'h0: seg = 7'b1000000;
- 4'h1: seg = 7'b1111001; // ---a----
- 4'h2: seg = 7'b0100100; // | |
- 4'h3: seg = 7'b0110000; // f b
- 4'h4: seg = 7'b0011001; // | |
- 4'h5: seg = 7'b0010010; // ---g----
- 4'h6: seg = 7'b0000010; // | |
- 4'h7: seg = 7'b1111000; // e c
- 4'h8: seg = 7'b0000000; // | |
- 4'h9: seg = 7'b0011000; // ---d----
- 4'ha: seg = 7'b0001000;
- 4'hb: seg = 7'b0000011;
- 4'hc: seg = 7'b1000110;
- 4'hd: seg = 7'b0100001;
- 4'he: seg = 7'b0000110;
- 4'hf: seg = 7'b0001110;
- endcase
- endmodule
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