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| 1 | ||
| 2 | library IEEE; | |
| 3 | use IEEE.STD_LOGIC_1164.all; | |
| 4 | use IEEE.STD_LOGIC_ARITH.all; | |
| 5 | - | entity main is |
| 5 | + | use IEEE.STD_LOGIC_UNSIGNED.all; |
| 6 | ||
| 7 | - | CLK, RESET, START: in std_logic; |
| 7 | + | entity CodeROM is |
| 8 | - | Result: out std_logic_vector(3 downto 0); |
| 8 | + | Generic( |
| 9 | - | Ready: out std_logic); |
| 9 | + | n:integer := 11; -- code word size |
| 10 | - | end main; |
| 10 | + | m:integer := 127; -- ROM length |
| 11 | k:integer := 7); -- adress bus size | |
| 12 | - | architecture mainArch of main is |
| 12 | + | |
| 13 | - | component CodeROM |
| 13 | + | Code_Read: in std_logic; |
| 14 | - | Generic( |
| 14 | + | Code_Adr: in std_logic_vector(k-1 downto 0); |
| 15 | - | n:integer := 11; -- code word size |
| 15 | + | Code_Out: out std_logic_vector(n-1 downto 0)); |
| 16 | - | m:integer := 127; -- ROM length |
| 16 | + | end CodeROM; |
| 17 | - | k:integer := 7); -- adress bus size |
| 17 | + | |
| 18 | - | Port( |
| 18 | + | architecture CodeROM_arch of CodeROM is |
| 19 | - | Code_Read: in std_logic; |
| 19 | + | subtype ROM_WORD is std_logic_vector(n-1 downto 0); |
| 20 | - | Code_Adr: in std_logic_vector(k-1 downto 0); |
| 20 | + | type ROM_TYPE is array(0 to m-1) of ROM_WORD; |
| 21 | - | Code_Out: out std_logic_vector(n-1 downto 0)); |
| 21 | + | signal Rom: ROM_TYPE := ( |
| 22 | - | end component; |
| 22 | + | "00000000000", -- push width |
| 23 | - | component DataRAM |
| 23 | + | "00000000001", -- push height |
| 24 | - | Generic( |
| 24 | + | "01110000000", -- mul |
| 25 | - | n:integer := 8; -- data word size |
| 25 | + | "00000000000", -- push width |
| 26 | - | m:integer := 64; -- RAM length |
| 26 | + | "10000000000", -- sub |
| 27 | - | k:integer := 6); -- adress bus size |
| 27 | + | "00010000001", -- pushc 1 |
| 28 | - | Port( |
| 28 | + | "10000000000", -- sub |
| 29 | - | Data_Read: in std_logic; |
| 29 | + | "00110000101", -- pop maxI |
| 30 | - | Data_Adr: in std_logic_vector(k-1 downto 0); |
| 30 | + | "00000000000", -- push width |
| 31 | - | Data_In: in std_logic_vector(n-1 downto 0); |
| 31 | + | "00010000001", -- pushc 1 |
| 32 | - | Data_Out: out std_logic_vector(n-1 downto 0)); |
| 32 | + | "01010000000", -- add |
| 33 | - | end component; |
| 33 | + | "00110000100", -- pop i |
| 34 | - | component MFSM |
| 34 | + | "00000000010", -- push source |
| 35 | - | Port( |
| 35 | + | "00110000111", -- pop topL |
| 36 | - | CLK, RESET, START: in std_logic; |
| 36 | + | "00000000010", -- push source |
| 37 | - | Ready: out std_logic; |
| 37 | + | "00010000001", -- pushc 1 |
| 38 | - | -- CodeROM ports: |
| 38 | + | "01100000000", -- addk |
| 39 | - | Code_Read: out std_logic; |
| 39 | + | "00110001000", -- pop top |
| 40 | - | Code_Adr: out std_logic_vector(6 downto 0); |
| 40 | + | "00010000010", -- pushc 2 |
| 41 | - | Code_In: in std_logic_vector(10 downto 0); |
| 41 | + | "01100000000", -- addk |
| 42 | - | -- DataRAM ports: |
| 42 | + | "00110001001", -- pop topR |
| 43 | - | Data_Read: out std_logic; |
| 43 | + | "00000000000", -- push width |
| 44 | - | Data_Adr: out std_logic_vector(5 downto 0); |
| 44 | + | "01100000000", -- addk |
| 45 | - | Data_In: in std_logic_vector(7 downto 0); |
| 45 | + | "00110001010", -- pop left |
| 46 | - | Data_Out: out std_logic_vector(7 downto 0)); |
| 46 | + | "00000000000", -- push width |
| 47 | - | end component; |
| 47 | + | "01100000000", -- addk |
| 48 | - | signal Data_Read, Code_Read: std_logic; |
| 48 | + | "00010000010", -- pushc 2 |
| 49 | - | signal Data_Adr: std_logic_vector(5 downto 0); |
| 49 | + | "01010000000", -- add |
| 50 | - | signal Data_In: std_logic_vector(7 downto 0); |
| 50 | + | "00110001011", -- pop right |
| 51 | - | signal Data_Out: std_logic_vector(7 downto 0); |
| 51 | + | "00000000000", -- push width |
| 52 | - | signal Code_Adr: std_logic_vector(6 downto 0); |
| 52 | + | "00010000010", -- pushc 2 |
| 53 | - | signal Code_In: std_logic_vector(10 downto 0); |
| 53 | + | "01110000000", -- mul |
| 54 | "01100000000", -- addk | |
| 55 | - | U1: CodeROM port map (Code_Read => Code_Read, Code_Adr => Code_Adr, Code_Out => Code_In); |
| 55 | + | "00110001100", -- pop botL |
| 56 | - | U2: DataRAM port map (Data_Read => Data_Read, Data_Adr => Data_Adr, Data_In => Data_Out, Data_Out => Data_In); |
| 56 | + | "00000000000", -- push width |
| 57 | - | U3: MFSM port map (CLK => CLK, RESET => RESET, START => START, Ready => Ready, |
| 57 | + | "00010000010", -- pushc 2 |
| 58 | - | Code_Read => Code_Read, Code_Adr => Code_Adr, Code_In => Code_In, |
| 58 | + | "01110000000", -- mul |
| 59 | - | Data_Read => Data_Read, Data_Adr => Data_Adr, Data_In => Data_In, Data_Out => Data_Out); |
| 59 | + | "01100000000", -- addk |
| 60 | - | end mainArch; |
| 60 | + | "00010000001", -- pushc 1 |
| 61 | "01010000000", -- add | |
| 62 | "00110001101", -- pop bot | |
| 63 | "00000000000", -- push width | |
| 64 | "00010000010", -- pushc 2 | |
| 65 | "01110000000", -- mul | |
| 66 | "01010000000", -- add | |
| 67 | "00010000010", -- pushc 2 | |
| 68 | "01010000000", -- add | |
| 69 | "00110001110", -- pop botR | |
| 70 | "00000000011", -- push dest | |
| 71 | "00000000100", -- push i | |
| 72 | "01010000000", -- add | |
| 73 | "00110000110", -- pop destAdr | |
| 74 | "00100000111", -- pushr topL | |
| 75 | "00100001001", -- pushr topR | |
| 76 | "10000000000", -- sub | |
| 77 | "00100001010", -- pushr left | |
| 78 | "00010000010", -- pushc 2 | |
| 79 | "01110000000", -- mul | |
| 80 | "01010000000", -- add | |
| 81 | "00100001011", -- pushr right | |
| 82 | "00010000010", -- pushc 2 | |
| 83 | "01110000000", -- mul | |
| 84 | "10000000000", -- sub | |
| 85 | "00100001100", -- pushr botL | |
| 86 | "01010000000", -- add | |
| 87 | "00100001110", -- pushr botR | |
| 88 | "10000000000", -- sub | |
| 89 | "10010000000", -- abs | |
| 90 | "00100001100", -- pushr botL | |
| 91 | "00100001101", -- pushr bot | |
| 92 | "00010000010", -- pushc 2 | |
| 93 | "01110000000", -- mul | |
| 94 | "01010000000", -- add | |
| 95 | "00100001110", -- pushr botR | |
| 96 | "01010000000", -- add | |
| 97 | "00100000111", -- pushr topL | |
| 98 | "10000000000", -- sub | |
| 99 | "00100001000", -- pushr top | |
| 100 | "00010000010", -- pushc 2 | |
| 101 | "01110000000", -- mul | |
| 102 | "10000000000", -- sub | |
| 103 | "00100001001", -- pushr topR | |
| 104 | "10000000000", -- sub | |
| 105 | "10010000000", -- abs | |
| 106 | "01010000000", -- add | |
| 107 | "01000000110", -- popr destAdr | |
| 108 | "00000000100", -- push i | |
| 109 | "00010000010", -- pushc 2 | |
| 110 | "01010000000", -- add | |
| 111 | "00000000000", -- push width | |
| 112 | "10100000000", -- mod | |
| 113 | "10111011110", -- jgz CONTINUE | |
| 114 | "00010000011", -- pushc 3 // Push Delta | |
| 115 | "11001011111", -- jmp END_IF | |
| 116 | "00010000001", -- pushc 1 // Push Delta | |
| 117 | "00000000111", -- push topL | |
| 118 | "01100000000", -- addk | |
| 119 | "00110000111", -- pop topL | |
| 120 | "00000001000", -- push top | |
| 121 | "01100000000", -- addk | |
| 122 | "00110001000", -- pop top | |
| 123 | "00000001001", -- push topR | |
| 124 | "01100000000", -- addk | |
| 125 | "00110001001", -- pop topR | |
| 126 | "00000001010", -- push left | |
| 127 | "01100000000", -- addk | |
| 128 | "00110001010", -- pop left | |
| 129 | "00000001011", -- push right | |
| 130 | "01100000000", -- addk | |
| 131 | "00110001011", -- pop right | |
| 132 | "00000001100", -- push botL | |
| 133 | "01100000000", -- addk | |
| 134 | "00110001100", -- pop botL | |
| 135 | "00000001101", -- push bot | |
| 136 | "01100000000", -- addk | |
| 137 | "00110001101", -- pop bot | |
| 138 | "00000001110", -- push botR | |
| 139 | "01100000000", -- addk | |
| 140 | "00110001110", -- pop botR | |
| 141 | "00000000100", -- push i | |
| 142 | "01010000000", -- add | |
| 143 | "00110000100", -- pop i | |
| 144 | "00000000101", -- push maxI | |
| 145 | "00000000100", -- push i | |
| 146 | "10000000000", -- sub | |
| 147 | "10110110000", -- jgz LOOP | |
| 148 | "11010000000");-- halt | |
| 149 | ||
| 150 | begin | |
| 151 | ||
| 152 | Main:process(Code_Read, Code_Adr) | |
| 153 | begin | |
| 154 | if (Code_Read = '1') then | |
| 155 | Code_Out <= Rom(CONV_INTEGER(Code_Adr)); | |
| 156 | end if; | |
| 157 | end process; | |
| 158 | ||
| 159 | end CodeROM_arch; |