library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity main is
    Port(
        CLK, RESET, START: in std_logic;
        Result: out std_logic_vector(3 downto 0);
        Ready: out std_logic);
end main;

architecture mainArch of main is
    component CodeROM
        Generic(
        n:integer := 11;  -- code word size
        m:integer := 127; -- ROM length
        k:integer := 7);  -- adress bus size
        Port(
        Code_Read: in std_logic;
        Code_Adr: in std_logic_vector(k-1 downto 0);
        Code_Out: out std_logic_vector(n-1 downto 0));
    end component;
    component DataRAM
        Generic(
        n:integer := 8;  -- data word size
        m:integer := 64; -- RAM length
        k:integer := 6); -- adress bus size
        Port(
        Data_Read: in std_logic;
        Data_Adr: in std_logic_vector(k-1 downto 0);
        Data_In: in std_logic_vector(n-1 downto 0);
        Data_Out: out std_logic_vector(n-1 downto 0));
    end component;
    component MFSM
        Port(
        CLK, RESET, START: in std_logic;
        Ready: out std_logic;
        -- CodeROM ports:
        Code_Read: out std_logic;
        Code_Adr: out std_logic_vector(6 downto 0);
        Code_In: in std_logic_vector(10 downto 0);
        -- DataRAM ports:
        Data_Read: out std_logic;
        Data_Adr: out std_logic_vector(5 downto 0);
        Data_In: in std_logic_vector(7 downto 0);
        Data_Out: out std_logic_vector(7 downto 0));
    end component;
    signal Data_Read, Code_Read: std_logic;
    signal Data_Adr: std_logic_vector(5 downto 0);
    signal Data_In: std_logic_vector(7 downto 0);
    signal Data_Out: std_logic_vector(7 downto 0);
    signal Code_Adr: std_logic_vector(6 downto 0);
    signal Code_In: std_logic_vector(10 downto 0);
begin
    U1: CodeROM port map (Code_Read => Code_Read, Code_Adr => Code_Adr, Code_Out => Code_In);
    U2: DataRAM port map (Data_Read => Data_Read, Data_Adr => Data_Adr, Data_In => Data_Out, Data_Out => Data_In);
    U3: MFSM port map (CLK => CLK, RESET => RESET, START => START, Ready => Ready,
        Code_Read => Code_Read, Code_Adr => Code_Adr, Code_In => Code_In,
        Data_Read => Data_Read, Data_Adr => Data_Adr, Data_In => Data_In, Data_Out => Data_Out);
end mainArch;