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| 1 | library IEEE; | |
| 2 | use IEEE.STD_LOGIC_1164.ALL; | |
| 3 | use IEEE.STD_LOGIC_ARITH.ALL; | |
| 4 | use IEEE.STD_LOGIC_UNSIGNED.ALL; | |
| 5 | ||
| 6 | entity MUX_2_1 is | |
| 7 | Port ( a,b,S : in std_logic; | |
| 8 | O : out std_logic; | |
| 9 | end MUX_2_1; | |
| 10 | ||
| 11 | architecture Behavioral of MUX_2_1 is | |
| 12 | P1: process (a, b, S) | |
| 13 | - | begin |
| 13 | + | begin |
| 14 | - | if (S='0') then |
| 14 | + | if (S = '0' ) then |
| 15 | - | O <= a; |
| 15 | + | O <= a; |
| 16 | else | |
| 17 | O <= b; | |
| 18 | - | end if; |
| 18 | + | end if; |
| 19 | ||
| 20 | end process P1; | |
| 21 | ||
| 22 | end Behavioral; |
