View difference between Paste ID: DQpHXb41 and 00jVjmDd

 library ieee;
-***Single Bit***
+use ieee.std_logic_1164.all;
 
-library IEEE;
+
-use IEEE.STD_LOGIC_1164.ALL;
+
-use IEEE.STD_LOGIC_ARITH.ALL;
+port(
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
+a: in std_logic;
 b: in std_logic;
--- Uncomment the following lines to use the declarations that are
+S: in std_logic;
--- provided for instantiating Xilinx primitive components.
+O: out std_logic
---library UNISIM;
+);
---use UNISIM.VComponents.all;
+
 
-entity ADDONE is
+
-Port ( a : in std_logic;
+
-b : in std_logic;
+with S select O <= a when '0', b when '1';
-cin : in std_logic;
+