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| 1 | //**************************************************************************** | |
| 2 | // Filename A4960.h | |
| 3 | //---------------------------------------------------------------------------- | |
| 4 | // Description This file contains definitions for the Registers of A4960 | |
| 5 | // | |
| 6 | //---------------------------------------------------------------------------- | |
| 7 | // Date 19.02.2013 | |
| 8 | // Author Thomas Hämmerle | |
| 9 | //**************************************************************************** | |
| 10 | ||
| 11 | #ifndef A4960_H_ | |
| 12 | #define A4960_H_ | |
| 13 | ||
| 14 | ||
| 15 | //configuration-register-addresses | |
| 16 | //**************************************************************************** | |
| 17 | #define A4960_CONFIG_REG_0 0x0000 //Blank- and Deadtime | |
| 18 | #define A4960_CONFIG_REG_1 0x2000 //Vref, Vdsth | |
| 19 | #define A4960_CONFIG_REG_2 0x4000 //PWM | |
| 20 | #define A4960_CONFIG_REG_3 0x6000 //Hold | |
| 21 | #define A4960_CONFIG_REG_4 0x8000 //Start Commutation | |
| 22 | #define A4960_CONFIG_REG_5 0xA000 //Ramp | |
| 23 | #define A4960_MASK_REG 0xC000 //Mask | |
| 24 | #define A4960_RUN_REG 0xE000 //Run | |
| 25 | //**************************************************************************** | |
| 26 | ||
| 27 | ||
| 28 | //read or write | |
| 29 | //**************************************************************************** | |
| 30 | #define A4960_READ 0x0000 | |
| 31 | #define A4960_WRITE 0x1000 | |
| 32 | //**************************************************************************** | |
| 33 | ||
| 34 | ||
| 35 | //configuration-register 0 | |
| 36 | //**************************************************************************** | |
| 37 | //Bits CB[1:0] | |
| 38 | #define A4960_CONF0_COMBLANKTIME_50us 0x0000 | |
| 39 | #define A4960_CONF0_COMBLANKTIME_100us 0x0400 | |
| 40 | #define A4960_CONF0_COMBLANKTIME_400us 0x0800 | |
| 41 | #define A4960_CONF0_COMBLANKTIME_1ms 0x0C00 | |
| 42 | ||
| 43 | //Bits BT[3:0] | |
| 44 | #define A4960_CONF0_BLANKTIME_0ns 0x0000 | |
| 45 | #define A4960_CONF0_BLANKTIME_400ns 0x0040 | |
| 46 | #define A4960_CONF0_BLANKTIME_800ns 0x0080 | |
| 47 | #define A4960_CONF0_BLANKTIME_1200ns 0x00C0 | |
| 48 | #define A4960_CONF0_BLANKTIME_1600ns 0x0100 | |
| 49 | #define A4960_CONF0_BLANKTIME_2000ns 0x0140 | |
| 50 | #define A4960_CONF0_BLANKTIME_2400ns 0x0180 | |
| 51 | #define A4960_CONF0_BLANKTIME_2800ns 0x01C0 | |
| 52 | #define A4960_CONF0_BLANKTIME_3200ns 0x0200 | |
| 53 | #define A4960_CONF0_BLANKTIME_3600ns 0x0240 | |
| 54 | #define A4960_CONF0_BLANKTIME_4000ns 0x0280 | |
| 55 | #define A4960_CONF0_BLANKTIME_4400ns 0x02C0 | |
| 56 | #define A4960_CONF0_BLANKTIME_4800ns 0x0300 | |
| 57 | #define A4960_CONF0_BLANKTIME_5200ns 0x0340 | |
| 58 | #define A4960_CONF0_BLANKTIME_5600ns 0x0380 | |
| 59 | #define A4960_CONF0_BLANKTIME_6000ns 0x03C0 | |
| 60 | ||
| 61 | //Bits DT[5:0] | |
| 62 | #define A4960_CONF0_DEADTIME_0ns 0x0000 | |
| 63 | #define A4960_CONF0_DEADTIME_50ns 0x0001 | |
| 64 | #define A4960_CONF0_DEADTIME_100ns 0x0002 | |
| 65 | #define A4960_CONF0_DEADTIME_150ns 0x0003 | |
| 66 | #define A4960_CONF0_DEADTIME_200ns 0x0004 | |
| 67 | #define A4960_CONF0_DEADTIME_250ns 0x0005 | |
| 68 | #define A4960_CONF0_DEADTIME_300ns 0x0006 | |
| 69 | #define A4960_CONF0_DEADTIME_350ns 0x0007 | |
| 70 | #define A4960_CONF0_DEADTIME_400ns 0x0008 | |
| 71 | #define A4960_CONF0_DEADTIME_450ns 0x0009 | |
| 72 | #define A4960_CONF0_DEADTIME_500ns 0x000A | |
| 73 | #define A4960_CONF0_DEADTIME_550ns 0x000B | |
| 74 | #define A4960_CONF0_DEADTIME_600ns 0x000C | |
| 75 | #define A4960_CONF0_DEADTIME_650ns 0x000D | |
| 76 | #define A4960_CONF0_DEADTIME_700ns 0x000E | |
| 77 | #define A4960_CONF0_DEADTIME_750ns 0x000F | |
| 78 | #define A4960_CONF0_DEADTIME_800ns 0x0010 | |
| 79 | #define A4960_CONF0_DEADTIME_850ns 0x0011 | |
| 80 | #define A4960_CONF0_DEADTIME_900ns 0x0012 | |
| 81 | #define A4960_CONF0_DEADTIME_950ns 0x0013 | |
| 82 | #define A4960_CONF0_DEADTIME_1000ns 0x0014 | |
| 83 | #define A4960_CONF0_DEADTIME_1050ns 0x0015 | |
| 84 | #define A4960_CONF0_DEADTIME_1100ns 0x0016 | |
| 85 | #define A4960_CONF0_DEADTIME_1150ns 0x0017 | |
| 86 | #define A4960_CONF0_DEADTIME_1200ns 0x0018 | |
| 87 | #define A4960_CONF0_DEADTIME_1250ns 0x0019 | |
| 88 | #define A4960_CONF0_DEADTIME_1300ns 0x001A | |
| 89 | #define A4960_CONF0_DEADTIME_1350ns 0x001B | |
| 90 | #define A4960_CONF0_DEADTIME_1400ns 0x001C | |
| 91 | #define A4960_CONF0_DEADTIME_1450ns 0x001D | |
| 92 | #define A4960_CONF0_DEADTIME_1500ns 0x001E | |
| 93 | #define A4960_CONF0_DEADTIME_1550ns 0x001F | |
| 94 | #define A4960_CONF0_DEADTIME_1600ns 0x0020 | |
| 95 | #define A4960_CONF0_DEADTIME_1650ns 0x0021 | |
| 96 | #define A4960_CONF0_DEADTIME_1700ns 0x0022 | |
| 97 | #define A4960_CONF0_DEADTIME_1750ns 0x0023 | |
| 98 | #define A4960_CONF0_DEADTIME_1800ns 0x0024 | |
| 99 | #define A4960_CONF0_DEADTIME_1850ns 0x0025 | |
| 100 | #define A4960_CONF0_DEADTIME_1900ns 0x0026 | |
| 101 | #define A4960_CONF0_DEADTIME_1950ns 0x0027 | |
| 102 | #define A4960_CONF0_DEADTIME_2000ns 0x0028 | |
| 103 | #define A4960_CONF0_DEADTIME_2050ns 0x0029 | |
| 104 | #define A4960_CONF0_DEADTIME_2100ns 0x002A | |
| 105 | #define A4960_CONF0_DEADTIME_2150ns 0x002B | |
| 106 | #define A4960_CONF0_DEADTIME_2200ns 0x002C | |
| 107 | #define A4960_CONF0_DEADTIME_2250ns 0x002D | |
| 108 | #define A4960_CONF0_DEADTIME_2300ns 0x002E | |
| 109 | #define A4960_CONF0_DEADTIME_2350ns 0x002F | |
| 110 | #define A4960_CONF0_DEADTIME_2400ns 0x0030 | |
| 111 | #define A4960_CONF0_DEADTIME_2450ns 0x0031 | |
| 112 | #define A4960_CONF0_DEADTIME_2500ns 0x0032 | |
| 113 | #define A4960_CONF0_DEADTIME_2550ns 0x0033 | |
| 114 | #define A4960_CONF0_DEADTIME_2600ns 0x0034 | |
| 115 | #define A4960_CONF0_DEADTIME_2650ns 0x0035 | |
| 116 | #define A4960_CONF0_DEADTIME_2700ns 0x0036 | |
| 117 | #define A4960_CONF0_DEADTIME_2750ns 0x0037 | |
| 118 | #define A4960_CONF0_DEADTIME_2800ns 0x0038 | |
| 119 | #define A4960_CONF0_DEADTIME_2850ns 0x0039 | |
| 120 | #define A4960_CONF0_DEADTIME_2900ns 0x003A | |
| 121 | #define A4960_CONF0_DEADTIME_2950ns 0x003B | |
| 122 | #define A4960_CONF0_DEADTIME_3000ns 0x003C | |
| 123 | #define A4960_CONF0_DEADTIME_3050ns 0x003D | |
| 124 | #define A4960_CONF0_DEADTIME_3100ns 0x003E | |
| 125 | #define A4960_CONF0_DEADTIME_3150ns 0x003F | |
| 126 | //**************************************************************************** | |
| 127 | //end configuration-register 0 | |
| 128 | ||
| 129 | ||
| 130 | //configuration-register 1 | |
| 131 | //**************************************************************************** | |
| 132 | //Bits VR[3:0] | |
| 133 | #define A4960_CONF1_CURRENT_6_25per 0x0000 | |
| 134 | #define A4960_CONF1_CURRENT_12_5per 0x0040 | |
| 135 | #define A4960_CONF1_CURRENT_18_75per 0x0080 | |
| 136 | #define A4960_CONF1_CURRENT_25_0per 0x00C0 | |
| 137 | #define A4960_CONF1_CURRENT_31_25per 0x0100 | |
| 138 | #define A4960_CONF1_CURRENT_37_5per 0x0140 | |
| 139 | #define A4960_CONF1_CURRENT_43_755per 0x0180 | |
| 140 | #define A4960_CONF1_CURRENT_50_0per 0x01C0 | |
| 141 | #define A4960_CONF1_CURRENT_56_25per 0x0200 | |
| 142 | #define A4960_CONF1_CURRENT_62_5per 0x0240 | |
| 143 | #define A4960_CONF1_CURRENT_68_75per 0x0280 | |
| 144 | #define A4960_CONF1_CURRENT_75_0per 0x02C0 | |
| 145 | #define A4960_CONF1_CURRENT_81_25per 0x0300 | |
| 146 | #define A4960_CONF1_CURRENT_87_5per 0x0340 | |
| 147 | #define A4960_CONF1_CURRENT_93_755per 0x0380 | |
| 148 | #define A4960_CONF1_CURRENT_100_0per 0x03C0 | |
| 149 | ||
| 150 | //Bits VT[5:0] | |
| 151 | #define A4960_CONF1_VDS_0mV 0x0000 | |
| 152 | #define A4960_CONF1_VDS_25mV 0x0001 | |
| 153 | #define A4960_CONF1_VDS_50mV 0x0002 | |
| 154 | #define A4960_CONF1_VDS_75mV 0x0003 | |
| 155 | #define A4960_CONF1_VDS_100mV 0x0004 | |
| 156 | #define A4960_CONF1_VDS_125mV 0x0005 | |
| 157 | #define A4960_CONF1_VDS_150mV 0x0006 | |
| 158 | #define A4960_CONF1_VDS_175mV 0x0007 | |
| 159 | #define A4960_CONF1_VDS_200mV 0x0008 | |
| 160 | #define A4960_CONF1_VDS_225mV 0x0009 | |
| 161 | #define A4960_CONF1_VDS_250mV 0x000A | |
| 162 | #define A4960_CONF1_VDS_275mV 0x000B | |
| 163 | #define A4960_CONF1_VDS_300mV 0x000C | |
| 164 | #define A4960_CONF1_VDS_325mV 0x000D | |
| 165 | #define A4960_CONF1_VDS_350mV 0x000E | |
| 166 | #define A4960_CONF1_VDS_375mV 0x000F | |
| 167 | #define A4960_CONF1_VDS_400mV 0x0010 | |
| 168 | #define A4960_CONF1_VDS_425mV 0x0011 | |
| 169 | #define A4960_CONF1_VDS_450mV 0x0012 | |
| 170 | #define A4960_CONF1_VDS_475mV 0x0013 | |
| 171 | #define A4960_CONF1_VDS_500mV 0x0014 | |
| 172 | #define A4960_CONF1_VDS_525mV 0x0015 | |
| 173 | #define A4960_CONF1_VDS_550mV 0x0016 | |
| 174 | #define A4960_CONF1_VDS_575mV 0x0017 | |
| 175 | #define A4960_CONF1_VDS_600mV 0x0018 | |
| 176 | #define A4960_CONF1_VDS_625mV 0x0019 | |
| 177 | #define A4960_CONF1_VDS_650mV 0x001A | |
| 178 | #define A4960_CONF1_VDS_675mV 0x001B | |
| 179 | #define A4960_CONF1_VDS_700mV 0x001C | |
| 180 | #define A4960_CONF1_VDS_725mV 0x001D | |
| 181 | #define A4960_CONF1_VDS_750mV 0x001E | |
| 182 | #define A4960_CONF1_VDS_775mV 0x001F | |
| 183 | #define A4960_CONF1_VDS_800mV 0x0020 | |
| 184 | #define A4960_CONF1_VDS_825mV 0x0021 | |
| 185 | #define A4960_CONF1_VDS_850mV 0x0022 | |
| 186 | #define A4960_CONF1_VDS_875mV 0x0023 | |
| 187 | #define A4960_CONF1_VDS_900mV 0x0024 | |
| 188 | #define A4960_CONF1_VDS_925mV 0x0025 | |
| 189 | #define A4960_CONF1_VDS_950mV 0x0026 | |
| 190 | #define A4960_CONF1_VDS_975mV 0x0027 | |
| 191 | #define A4960_CONF1_VDS_1000mV 0x0028 | |
| 192 | #define A4960_CONF1_VDS_1025mV 0x0029 | |
| 193 | #define A4960_CONF1_VDS_1050mV 0x002A | |
| 194 | #define A4960_CONF1_VDS_1075mV 0x002B | |
| 195 | #define A4960_CONF1_VDS_1100mV 0x002C | |
| 196 | #define A4960_CONF1_VDS_1125mV 0x002D | |
| 197 | #define A4960_CONF1_VDS_1150mV 0x002E | |
| 198 | #define A4960_CONF1_VDS_1175mV 0x002F | |
| 199 | #define A4960_CONF1_VDS_1200mV 0x0030 | |
| 200 | #define A4960_CONF1_VDS_1225mV 0x0031 | |
| 201 | #define A4960_CONF1_VDS_1250mV 0x0032 | |
| 202 | #define A4960_CONF1_VDS_1275mV 0x0033 | |
| 203 | #define A4960_CONF1_VDS_1300mV 0x0034 | |
| 204 | #define A4960_CONF1_VDS_1325mV 0x0035 | |
| 205 | #define A4960_CONF1_VDS_1350mV 0x0036 | |
| 206 | #define A4960_CONF1_VDS_1375mV 0x0037 | |
| 207 | #define A4960_CONF1_VDS_1400mV 0x0038 | |
| 208 | #define A4960_CONF1_VDS_1425mV 0x0039 | |
| 209 | #define A4960_CONF1_VDS_1450mV 0x003A | |
| 210 | #define A4960_CONF1_VDS_1475mV 0x003B | |
| 211 | #define A4960_CONF1_VDS_1500mV 0x003C | |
| 212 | #define A4960_CONF1_VDS_1525mV 0x003D | |
| 213 | #define A4960_CONF1_VDS_1550mV 0x003E | |
| 214 | #define A4960_CONF1_VDS_1575mV 0x003F | |
| 215 | //**************************************************************************** | |
| 216 | //end configuration-register 1 | |
| 217 | ||
| 218 | ||
| 219 | //configuration-register 2 | |
| 220 | //**************************************************************************** | |
| 221 | //Bits PT[4:0] | |
| 222 | #define A4960_CONF2_OFFTIME_10_0us 0x0000 | |
| 223 | #define A4960_CONF2_OFFTIME_11_6us 0x0001 | |
| 224 | #define A4960_CONF2_OFFTIME_13_2us 0x0002 | |
| 225 | #define A4960_CONF2_OFFTIME_14_8us 0x0003 | |
| 226 | #define A4960_CONF2_OFFTIME_16_4us 0x0004 | |
| 227 | #define A4960_CONF2_OFFTIME_18_0us 0x0005 | |
| 228 | #define A4960_CONF2_OFFTIME_19_6us 0x0006 | |
| 229 | #define A4960_CONF2_OFFTIME_21_2us 0x0007 | |
| 230 | #define A4960_CONF2_OFFTIME_22_8us 0x0008 | |
| 231 | #define A4960_CONF2_OFFTIME_24_4us 0x0009 | |
| 232 | #define A4960_CONF2_OFFTIME_26_0us 0x000A | |
| 233 | #define A4960_CONF2_OFFTIME_27_6us 0x000B | |
| 234 | #define A4960_CONF2_OFFTIME_29_2us 0x000C | |
| 235 | #define A4960_CONF2_OFFTIME_30_8us 0x000D | |
| 236 | #define A4960_CONF2_OFFTIME_32_4us 0x000E | |
| 237 | #define A4960_CONF2_OFFTIME_34_0us 0x000F | |
| 238 | #define A4960_CONF2_OFFTIME_35_6us 0x0010 | |
| 239 | #define A4960_CONF2_OFFTIME_37_2us 0x0011 | |
| 240 | #define A4960_CONF2_OFFTIME_38_8us 0x0012 | |
| 241 | #define A4960_CONF2_OFFTIME_40_4us 0x0013 | |
| 242 | #define A4960_CONF2_OFFTIME_42_0us 0x0014 | |
| 243 | #define A4960_CONF2_OFFTIME_43_6us 0x0015 | |
| 244 | #define A4960_CONF2_OFFTIME_45_2us 0x0016 | |
| 245 | #define A4960_CONF2_OFFTIME_46_8us 0x0017 | |
| 246 | #define A4960_CONF2_OFFTIME_48_4us 0x0018 | |
| 247 | #define A4960_CONF2_OFFTIME_50_0us 0x0019 | |
| 248 | #define A4960_CONF2_OFFTIME_51_6us 0x001A | |
| 249 | #define A4960_CONF2_OFFTIME_53_2us 0x001B | |
| 250 | #define A4960_CONF2_OFFTIME_54_8us 0x001C | |
| 251 | #define A4960_CONF2_OFFTIME_56_4us 0x001D | |
| 252 | #define A4960_CONF2_OFFTIME_58_0us 0x001E | |
| 253 | #define A4960_CONF2_OFFTIME_59_6us 0x001F | |
| 254 | //**************************************************************************** | |
| 255 | //end configuration-register 2 | |
| 256 | ||
| 257 | ||
| 258 | //configuration-register 3 | |
| 259 | //**************************************************************************** | |
| 260 | //Bits IDS | |
| 261 | #define A4960_CONF3_CURRENT_LIMIT 0x0000 | |
| 262 | #define A4960_CONF3_DUTYCYCLE_LIMIT 0x0100 | |
| 263 | ||
| 264 | //Bits HQ[3:0] | |
| 265 | #define A4960_CONF3_STARTTORQUE_6_25per 0x0000 | |
| 266 | #define A4960_CONF3_STARTTORQUE_12_5per 0x0010 | |
| 267 | #define A4960_CONF3_STARTTORQUE_18_75per 0x0020 | |
| 268 | #define A4960_CONF3_STARTTORQUE_25_0per 0x0030 | |
| 269 | #define A4960_CONF3_STARTTORQUE_31_25per 0x0040 | |
| 270 | #define A4960_CONF3_STARTTORQUE_37_5per 0x0050 | |
| 271 | #define A4960_CONF3_STARTTORQUE_43_755per 0x0060 | |
| 272 | #define A4960_CONF3_STARTTORQUE_50_0per 0x0070 | |
| 273 | #define A4960_CONF3_STARTTORQUE_56_25per 0x0080 | |
| 274 | #define A4960_CONF3_STARTTORQUE_62_5per 0x0090 | |
| 275 | #define A4960_CONF3_STARTTORQUE_68_75per 0x00A0 | |
| 276 | #define A4960_CONF3_STARTTORQUE_75_0per 0x00B0 | |
| 277 | #define A4960_CONF3_STARTTORQUE_81_25per 0x00C0 | |
| 278 | #define A4960_CONF3_STARTTORQUE_87_5per 0x00D0 | |
| 279 | #define A4960_CONF3_STARTTORQUE_93_755per 0x00E0 | |
| 280 | #define A4960_CONF3_STARTTORQUE_100_0per 0x00F0 | |
| 281 | ||
| 282 | //Bits HT[3:0] | |
| 283 | #define A4960_CONF3_HOLDTIME_2ms 0x0000 | |
| 284 | #define A4960_CONF3_HOLDTIME_10ms 0x0001 | |
| 285 | #define A4960_CONF3_HOLDTIME_18ms 0x0002 | |
| 286 | #define A4960_CONF3_HOLDTIME_26ms 0x0003 | |
| 287 | #define A4960_CONF3_HOLDTIME_34ms 0x0004 | |
| 288 | #define A4960_CONF3_HOLDTIME_42ms 0x0005 | |
| 289 | #define A4960_CONF3_HOLDTIME_50ms 0x0006 | |
| 290 | #define A4960_CONF3_HOLDTIME_58ms 0x0007 | |
| 291 | #define A4960_CONF3_HOLDTIME_66ms 0x0008 | |
| 292 | #define A4960_CONF3_HOLDTIME_74ms 0x0009 | |
| 293 | #define A4960_CONF3_HOLDTIME_82ms 0x000A | |
| 294 | #define A4960_CONF3_HOLDTIME_90ms 0x000B | |
| 295 | #define A4960_CONF3_HOLDTIME_98ms 0x000C | |
| 296 | #define A4960_CONF3_HOLDTIME_106ms 0x000D | |
| 297 | #define A4960_CONF3_HOLDTIME_114ms 0x000E | |
| 298 | #define A4960_CONF3_HOLDTIME_122ms 0x000F | |
| 299 | //**************************************************************************** | |
| 300 | //end configuration-register 3 | |
| 301 | ||
| 302 | ||
| 303 | //configuration-register 4 | |
| 304 | //**************************************************************************** | |
| 305 | //Bits EC[3:0] | |
| 306 | #define A4960_CONF4_ENDCOMMUTIME_200ns 0x0000 | |
| 307 | #define A4960_CONF4_ENDCOMMUTIME_400ns 0x0010 | |
| 308 | #define A4960_CONF4_ENDCOMMUTIME_600ns 0x0020 | |
| 309 | #define A4960_CONF4_ENDCOMMUTIME_800ns 0x0030 | |
| 310 | #define A4960_CONF4_ENDCOMMUTIME_1000ns 0x0040 | |
| 311 | #define A4960_CONF4_ENDCOMMUTIME_1200ns 0x0050 | |
| 312 | #define A4960_CONF4_ENDCOMMUTIME_1400ns 0x0060 | |
| 313 | #define A4960_CONF4_ENDCOMMUTIME_1600ns 0x0070 | |
| 314 | #define A4960_CONF4_ENDCOMMUTIME_1800ns 0x0080 | |
| 315 | #define A4960_CONF4_ENDCOMMUTIME_2000ns 0x0090 | |
| 316 | #define A4960_CONF4_ENDCOMMUTIME_2200ns 0x00A0 | |
| 317 | #define A4960_CONF4_ENDCOMMUTIME_2400ns 0x00B0 | |
| 318 | #define A4960_CONF4_ENDCOMMUTIME_2600ns 0x00C0 | |
| 319 | #define A4960_CONF4_ENDCOMMUTIME_2800ns 0x00D0 | |
| 320 | #define A4960_CONF4_ENDCOMMUTIME_3000ns 0x00E0 | |
| 321 | #define A4960_CONF4_ENDCOMMUTIME_3200ns 0x00F0 | |
| 322 | ||
| 323 | //Bits SC[3:0] | |
| 324 | #define A4960_CONF4_STARTCOMMUTIME_8ms 0x0000 | |
| 325 | #define A4960_CONF4_STARTCOMMUTIME_16ms 0x0001 | |
| 326 | #define A4960_CONF4_STARTCOMMUTIME_24ms 0x0002 | |
| 327 | #define A4960_CONF4_STARTCOMMUTIME_32ms 0x0003 | |
| 328 | #define A4960_CONF4_STARTCOMMUTIME_40ms 0x0004 | |
| 329 | #define A4960_CONF4_STARTCOMMUTIME_48ms 0x0005 | |
| 330 | #define A4960_CONF4_STARTCOMMUTIME_56ms 0x0006 | |
| 331 | #define A4960_CONF4_STARTCOMMUTIME_64ms 0x0007 | |
| 332 | #define A4960_CONF4_STARTCOMMUTIME_72ms 0x0008 | |
| 333 | #define A4960_CONF4_STARTCOMMUTIME_80ms 0x0009 | |
| 334 | #define A4960_CONF4_STARTCOMMUTIME_88ms 0x000A | |
| 335 | #define A4960_CONF4_STARTCOMMUTIME_96ms 0x000B | |
| 336 | #define A4960_CONF4_STARTCOMMUTIME_104ms 0x000C | |
| 337 | #define A4960_CONF4_STARTCOMMUTIME_112ms 0x000D | |
| 338 | #define A4960_CONF4_STARTCOMMUTIME_120ms 0x000E | |
| 339 | #define A4960_CONF4_STARTCOMMUTIME_128ms 0x000F | |
| 340 | //**************************************************************************** | |
| 341 | //end configuration-register 4 | |
| 342 | ||
| 343 | ||
| 344 | //configuration-register 5 | |
| 345 | //**************************************************************************** | |
| 346 | //Bits PA[3:0] | |
| 347 | #define A4960_CONF5_PHASEADVANCE_0 0x0000 | |
| 348 | #define A4960_CONF5_PHASEADVANCE_1_875 0x0100 | |
| 349 | #define A4960_CONF5_PHASEADVANCE_3_750 0x0200 | |
| 350 | #define A4960_CONF5_PHASEADVANCE_5_625 0x0300 | |
| 351 | #define A4960_CONF5_PHASEADVANCE_7_500 0x0400 | |
| 352 | #define A4960_CONF5_PHASEADVANCE_9_375 0x0500 | |
| 353 | #define A4960_CONF5_PHASEADVANCE_11_250 0x0600 | |
| 354 | #define A4960_CONF5_PHASEADVANCE_13_125 0x0700 | |
| 355 | #define A4960_CONF5_PHASEADVANCE_15_000 0x0800 | |
| 356 | #define A4960_CONF5_PHASEADVANCE_16_875 0x0900 | |
| 357 | #define A4960_CONF5_PHASEADVANCE_18_750 0x0A00 | |
| 358 | #define A4960_CONF5_PHASEADVANCE_20_625 0x0B00 | |
| 359 | #define A4960_CONF5_PHASEADVANCE_22_500 0x0C00 | |
| 360 | #define A4960_CONF5_PHASEADVANCE_24_375 0x0D00 | |
| 361 | #define A4960_CONF5_PHASEADVANCE_26_250 0x0E00 | |
| 362 | #define A4960_CONF5_PHASEADVANCE_28_125 0x0F00 | |
| 363 | ||
| 364 | //Bits RQ[3:0] | |
| 365 | #define A4960_CONF5_RAMPTORQUE_6_25per 0x0000 | |
| 366 | #define A4960_CONF5_RAMPTORQUE_12_5per 0x0010 | |
| 367 | #define A4960_CONF5_RAMPTORQUE_18_75per 0x0020 | |
| 368 | #define A4960_CONF5_RAMPTORQUE_25_0per 0x0030 | |
| 369 | #define A4960_CONF5_RAMPTORQUE_31_25per 0x0040 | |
| 370 | #define A4960_CONF5_RAMPTORQUE_37_5per 0x0050 | |
| 371 | #define A4960_CONF5_RAMPTORQUE_43_755per 0x0060 | |
| 372 | #define A4960_CONF5_RAMPTORQUE_50_0per 0x0070 | |
| 373 | #define A4960_CONF5_RAMPTORQUE_56_25per 0x0080 | |
| 374 | #define A4960_CONF5_RAMPTORQUE_62_5per 0x0090 | |
| 375 | #define A4960_CONF5_RAMPTORQUE_68_75per 0x00A0 | |
| 376 | #define A4960_CONF5_RAMPTORQUE_75_0per 0x00B0 | |
| 377 | #define A4960_CONF5_RAMPTORQUE_81_25per 0x00C0 | |
| 378 | #define A4960_CONF5_RAMPTORQUE_87_5per 0x00D0 | |
| 379 | #define A4960_CONF5_RAMPTORQUE_93_755per 0x00E0 | |
| 380 | #define A4960_CONF5_RAMPTORQUE_100_0per 0x00F0 | |
| 381 | ||
| 382 | //Bits RR[3:0] | |
| 383 | #define A4960_CONF5_RAMPRATE_200ns 0x0000 | |
| 384 | #define A4960_CONF5_RAMPRATE_400ns 0x0001 | |
| 385 | #define A4960_CONF5_RAMPRATE_600ns 0x0002 | |
| 386 | #define A4960_CONF5_RAMPRATE_800ns 0x0003 | |
| 387 | #define A4960_CONF5_RAMPRATE_1000ns 0x0004 | |
| 388 | #define A4960_CONF5_RAMPRATE_1200ns 0x0005 | |
| 389 | #define A4960_CONF5_RAMPRATE_1400ns 0x0006 | |
| 390 | #define A4960_CONF5_RAMPRATE_1600ns 0x0007 | |
| 391 | #define A4960_CONF5_RAMPRATE_1800ns 0x0008 | |
| 392 | #define A4960_CONF5_RAMPRATE_2000ns 0x0009 | |
| 393 | #define A4960_CONF5_RAMPRATE_2200ns 0x000A | |
| 394 | #define A4960_CONF5_RAMPRATE_2400ns 0x000B | |
| 395 | #define A4960_CONF5_RAMPRATE_2600ns 0x000C | |
| 396 | #define A4960_CONF5_RAMPRATE_2800ns 0x000D | |
| 397 | #define A4960_CONF5_RAMPRATE_3000ns 0x000E | |
| 398 | #define A4960_CONF5_RAMPRATE_3200ns 0x000F | |
| 399 | //**************************************************************************** | |
| 400 | //end configuration-register 5 | |
| 401 | ||
| 402 | ||
| 403 | //Run-Register | |
| 404 | //**************************************************************************** | |
| 405 | //Bits BH[1:0] | |
| 406 | #define A4960_RUN_HYSTERESIS_AUTO 0x0000 | |
| 407 | - | #define A4960_RUN_HYSTERESIS_AUTO 0x0400 |
| 407 | + | #define A4960_RUN_HYSTERESIS_NONE 0x0400 |
| 408 | - | #define A4960_RUN_HYSTERESIS_AUTO 0x0800 |
| 408 | + | #define A4960_RUN_HYSTERESIS_HIGH 0x0800 |
| 409 | - | #define A4960_RUN_HYSTERESIS_AUTO 0x0C00 |
| 409 | + | #define A4960_RUN_HYSTERESIS_LOW 0x0C00 |
| 410 | ||
| 411 | //Bits BW[2:0] | |
| 412 | #define A4960_RUN_BEMFWINDOW_400ns 0x0000 | |
| 413 | #define A4960_RUN_BEMFWINDOW_800ns 0x0080 | |
| 414 | #define A4960_RUN_BEMFWINDOW_1600ns 0x0100 | |
| 415 | #define A4960_RUN_BEMFWINDOW_3200ns 0x0180 | |
| 416 | #define A4960_RUN_BEMFWINDOW_6400ns 0x0200 | |
| 417 | #define A4960_RUN_BEMFWINDOW_12800ns 0x0280 | |
| 418 | #define A4960_RUN_BEMFWINDOW_25600ns 0x0300 | |
| 419 | #define A4960_RUN_BEMFWINDOW_51200ns 0x0380 | |
| 420 | ||
| 421 | //Bit ESF | |
| 422 | #define A4960_RUN_STOPONFAIL_ENABLE 0x0040 | |
| 423 | #define A4960_RUN_STOPONFAIL_DISABLE 0x0000 | |
| 424 | ||
| 425 | //Bits DG[1:0] | |
| 426 | #define A4960_RUN_DIAGPIN_FAULT 0x0000 | |
| 427 | #define A4960_RUN_DIAGPIN_LOS 0x0010 | |
| 428 | #define A4960_RUN_DIAGPIN_VDSTH 0x0020 | |
| 429 | #define A4960_RUN_DIAGPIN_CLK 0x0030 | |
| 430 | ||
| 431 | //Bit RSC | |
| 432 | #define A4960_RUN_RESTART_ENABLE 0x0008 | |
| 433 | #define A4960_RUN_RESTART_DISABLE 0x0000 | |
| 434 | ||
| 435 | //Bit BRK | |
| 436 | #define A4960_RUN_BRAKE_NORMAL 0x0000 | |
| 437 | #define A4960_RUN_BRAKE_SLOW 0x0004 | |
| 438 | ||
| 439 | //Bit DIR | |
| 440 | #define A4960_RUN_DIRECTION_FORWARD 0x0000 | |
| 441 | #define A4960_RUN_DIRECTION_REVERSE 0x0002 | |
| 442 | ||
| 443 | //Bit RUN | |
| 444 | #define A4960_RUN_RUN_COAST 0x0000 | |
| 445 | #define A4960_RUN_RUN_START 0x0001 | |
| 446 | //**************************************************************************** | |
| 447 | ||
| 448 | ||
| 449 | ||
| 450 | //Mask-Register | |
| 451 | //**************************************************************************** | |
| 452 | #define A4960_MASK_TEMPWARNING 0x0800 | |
| 453 | #define A4960_MASK_THERMALSUHTDOWN 0x0400 | |
| 454 | #define A4960_MASK_LOSSOFBEMF 0x0200 | |
| 455 | #define A4960_MASK_BOOTCAPA 0x0100 | |
| 456 | #define A4960_MASK_BOOTCAPB 0x0080 | |
| 457 | #define A4960_MASK_BOOTCAPC 0x0040 | |
| 458 | #define A4960_MASK_PHASEAHIGH 0x0020 | |
| 459 | #define A4960_MASK_PHASEALOW 0x0010 | |
| 460 | #define A4960_MASK_PHASEBHIGH 0x0008 | |
| 461 | #define A4960_MASK_PHASEBLOW 0x0004 | |
| 462 | #define A4960_MASK_PHASECHIGH 0x0002 | |
| 463 | #define A4960_MASK_PHASECLOW 0x0001 | |
| 464 | //**************************************************************************** | |
| 465 | ||
| 466 | //Diagnostic-Register | |
| 467 | //**************************************************************************** | |
| 468 | #define A4960_DIAG_GENERALFAULT 0x8000 | |
| 469 | #define A4960_DIAG_POWERONRST 0x4000 | |
| 470 | #define A4960_DIAG_UNDERVOLTAGE 0x2000 | |
| 471 | #define A4960_DIAG_HIGHTEMP 0x0800 | |
| 472 | #define A4960_DIAG_OVERTEMPSD 0x0400 | |
| 473 | #define A4960_DIAG_BEMFSYNCLOST 0x0200 | |
| 474 | #define A4960_DIAG_BOOTCAPA 0x0100 | |
| 475 | #define A4960_DIAG_BOOTCAPB 0x0080 | |
| 476 | #define A4960_DIAG_BOOTCAPC 0x0040 | |
| 477 | #define A4960_DIAG_PHASEAHIGH_FAULT 0x0020 | |
| 478 | #define A4960_DIAG_PHASEALOW_FAULT 0x0010 | |
| 479 | #define A4960_DIAG_PHASEBHIGH_FAULT 0x0008 | |
| 480 | #define A4960_DIAG_PHASEBLOW_FAULT 0x0004 | |
| 481 | #define A4960_DIAG_PHASECHIGH_FAULT 0x0002 | |
| 482 | #define A4960_DIAG_PHASEVLOW_FAULT 0x0001 | |
| 483 | //**************************************************************************** | |
| 484 | ||
| 485 | ||
| 486 | #endif /* A4960_H_ */ |
