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- //****************************************************************************
- // Filename A4960.h
- //----------------------------------------------------------------------------
- // Description This file contains definitions for the Registers of A4960
- //
- //----------------------------------------------------------------------------
- // Date 19.02.2013
- // Author Thomas Hämmerle
- //****************************************************************************
- #ifndef A4960_H_
- #define A4960_H_
- //configuration-register-addresses
- //****************************************************************************
- #define A4960_CONFIG_REG_0 0x0000 //Blank- and Deadtime
- #define A4960_CONFIG_REG_1 0x2000 //Vref, Vdsth
- #define A4960_CONFIG_REG_2 0x4000 //PWM
- #define A4960_CONFIG_REG_3 0x6000 //Hold
- #define A4960_CONFIG_REG_4 0x8000 //Start Commutation
- #define A4960_CONFIG_REG_5 0xA000 //Ramp
- #define A4960_MASK_REG 0xC000 //Mask
- #define A4960_RUN_REG 0xE000 //Run
- //****************************************************************************
- //read or write
- //****************************************************************************
- #define A4960_READ 0x0000
- #define A4960_WRITE 0x1000
- //****************************************************************************
- //configuration-register 0
- //****************************************************************************
- //Bits CB[1:0]
- #define A4960_CONF0_COMBLANKTIME_50us 0x0000
- #define A4960_CONF0_COMBLANKTIME_100us 0x0400
- #define A4960_CONF0_COMBLANKTIME_400us 0x0800
- #define A4960_CONF0_COMBLANKTIME_1ms 0x0C00
- //Bits BT[3:0]
- #define A4960_CONF0_BLANKTIME_0ns 0x0000
- #define A4960_CONF0_BLANKTIME_400ns 0x0040
- #define A4960_CONF0_BLANKTIME_800ns 0x0080
- #define A4960_CONF0_BLANKTIME_1200ns 0x00C0
- #define A4960_CONF0_BLANKTIME_1600ns 0x0100
- #define A4960_CONF0_BLANKTIME_2000ns 0x0140
- #define A4960_CONF0_BLANKTIME_2400ns 0x0180
- #define A4960_CONF0_BLANKTIME_2800ns 0x01C0
- #define A4960_CONF0_BLANKTIME_3200ns 0x0200
- #define A4960_CONF0_BLANKTIME_3600ns 0x0240
- #define A4960_CONF0_BLANKTIME_4000ns 0x0280
- #define A4960_CONF0_BLANKTIME_4400ns 0x02C0
- #define A4960_CONF0_BLANKTIME_4800ns 0x0300
- #define A4960_CONF0_BLANKTIME_5200ns 0x0340
- #define A4960_CONF0_BLANKTIME_5600ns 0x0380
- #define A4960_CONF0_BLANKTIME_6000ns 0x03C0
- //Bits DT[5:0]
- #define A4960_CONF0_DEADTIME_0ns 0x0000
- #define A4960_CONF0_DEADTIME_50ns 0x0001
- #define A4960_CONF0_DEADTIME_100ns 0x0002
- #define A4960_CONF0_DEADTIME_150ns 0x0003
- #define A4960_CONF0_DEADTIME_200ns 0x0004
- #define A4960_CONF0_DEADTIME_250ns 0x0005
- #define A4960_CONF0_DEADTIME_300ns 0x0006
- #define A4960_CONF0_DEADTIME_350ns 0x0007
- #define A4960_CONF0_DEADTIME_400ns 0x0008
- #define A4960_CONF0_DEADTIME_450ns 0x0009
- #define A4960_CONF0_DEADTIME_500ns 0x000A
- #define A4960_CONF0_DEADTIME_550ns 0x000B
- #define A4960_CONF0_DEADTIME_600ns 0x000C
- #define A4960_CONF0_DEADTIME_650ns 0x000D
- #define A4960_CONF0_DEADTIME_700ns 0x000E
- #define A4960_CONF0_DEADTIME_750ns 0x000F
- #define A4960_CONF0_DEADTIME_800ns 0x0010
- #define A4960_CONF0_DEADTIME_850ns 0x0011
- #define A4960_CONF0_DEADTIME_900ns 0x0012
- #define A4960_CONF0_DEADTIME_950ns 0x0013
- #define A4960_CONF0_DEADTIME_1000ns 0x0014
- #define A4960_CONF0_DEADTIME_1050ns 0x0015
- #define A4960_CONF0_DEADTIME_1100ns 0x0016
- #define A4960_CONF0_DEADTIME_1150ns 0x0017
- #define A4960_CONF0_DEADTIME_1200ns 0x0018
- #define A4960_CONF0_DEADTIME_1250ns 0x0019
- #define A4960_CONF0_DEADTIME_1300ns 0x001A
- #define A4960_CONF0_DEADTIME_1350ns 0x001B
- #define A4960_CONF0_DEADTIME_1400ns 0x001C
- #define A4960_CONF0_DEADTIME_1450ns 0x001D
- #define A4960_CONF0_DEADTIME_1500ns 0x001E
- #define A4960_CONF0_DEADTIME_1550ns 0x001F
- #define A4960_CONF0_DEADTIME_1600ns 0x0020
- #define A4960_CONF0_DEADTIME_1650ns 0x0021
- #define A4960_CONF0_DEADTIME_1700ns 0x0022
- #define A4960_CONF0_DEADTIME_1750ns 0x0023
- #define A4960_CONF0_DEADTIME_1800ns 0x0024
- #define A4960_CONF0_DEADTIME_1850ns 0x0025
- #define A4960_CONF0_DEADTIME_1900ns 0x0026
- #define A4960_CONF0_DEADTIME_1950ns 0x0027
- #define A4960_CONF0_DEADTIME_2000ns 0x0028
- #define A4960_CONF0_DEADTIME_2050ns 0x0029
- #define A4960_CONF0_DEADTIME_2100ns 0x002A
- #define A4960_CONF0_DEADTIME_2150ns 0x002B
- #define A4960_CONF0_DEADTIME_2200ns 0x002C
- #define A4960_CONF0_DEADTIME_2250ns 0x002D
- #define A4960_CONF0_DEADTIME_2300ns 0x002E
- #define A4960_CONF0_DEADTIME_2350ns 0x002F
- #define A4960_CONF0_DEADTIME_2400ns 0x0030
- #define A4960_CONF0_DEADTIME_2450ns 0x0031
- #define A4960_CONF0_DEADTIME_2500ns 0x0032
- #define A4960_CONF0_DEADTIME_2550ns 0x0033
- #define A4960_CONF0_DEADTIME_2600ns 0x0034
- #define A4960_CONF0_DEADTIME_2650ns 0x0035
- #define A4960_CONF0_DEADTIME_2700ns 0x0036
- #define A4960_CONF0_DEADTIME_2750ns 0x0037
- #define A4960_CONF0_DEADTIME_2800ns 0x0038
- #define A4960_CONF0_DEADTIME_2850ns 0x0039
- #define A4960_CONF0_DEADTIME_2900ns 0x003A
- #define A4960_CONF0_DEADTIME_2950ns 0x003B
- #define A4960_CONF0_DEADTIME_3000ns 0x003C
- #define A4960_CONF0_DEADTIME_3050ns 0x003D
- #define A4960_CONF0_DEADTIME_3100ns 0x003E
- #define A4960_CONF0_DEADTIME_3150ns 0x003F
- //****************************************************************************
- //end configuration-register 0
- //configuration-register 1
- //****************************************************************************
- //Bits VR[3:0]
- #define A4960_CONF1_CURRENT_6_25per 0x0000
- #define A4960_CONF1_CURRENT_12_5per 0x0040
- #define A4960_CONF1_CURRENT_18_75per 0x0080
- #define A4960_CONF1_CURRENT_25_0per 0x00C0
- #define A4960_CONF1_CURRENT_31_25per 0x0100
- #define A4960_CONF1_CURRENT_37_5per 0x0140
- #define A4960_CONF1_CURRENT_43_755per 0x0180
- #define A4960_CONF1_CURRENT_50_0per 0x01C0
- #define A4960_CONF1_CURRENT_56_25per 0x0200
- #define A4960_CONF1_CURRENT_62_5per 0x0240
- #define A4960_CONF1_CURRENT_68_75per 0x0280
- #define A4960_CONF1_CURRENT_75_0per 0x02C0
- #define A4960_CONF1_CURRENT_81_25per 0x0300
- #define A4960_CONF1_CURRENT_87_5per 0x0340
- #define A4960_CONF1_CURRENT_93_755per 0x0380
- #define A4960_CONF1_CURRENT_100_0per 0x03C0
- //Bits VT[5:0]
- #define A4960_CONF1_VDS_0mV 0x0000
- #define A4960_CONF1_VDS_25mV 0x0001
- #define A4960_CONF1_VDS_50mV 0x0002
- #define A4960_CONF1_VDS_75mV 0x0003
- #define A4960_CONF1_VDS_100mV 0x0004
- #define A4960_CONF1_VDS_125mV 0x0005
- #define A4960_CONF1_VDS_150mV 0x0006
- #define A4960_CONF1_VDS_175mV 0x0007
- #define A4960_CONF1_VDS_200mV 0x0008
- #define A4960_CONF1_VDS_225mV 0x0009
- #define A4960_CONF1_VDS_250mV 0x000A
- #define A4960_CONF1_VDS_275mV 0x000B
- #define A4960_CONF1_VDS_300mV 0x000C
- #define A4960_CONF1_VDS_325mV 0x000D
- #define A4960_CONF1_VDS_350mV 0x000E
- #define A4960_CONF1_VDS_375mV 0x000F
- #define A4960_CONF1_VDS_400mV 0x0010
- #define A4960_CONF1_VDS_425mV 0x0011
- #define A4960_CONF1_VDS_450mV 0x0012
- #define A4960_CONF1_VDS_475mV 0x0013
- #define A4960_CONF1_VDS_500mV 0x0014
- #define A4960_CONF1_VDS_525mV 0x0015
- #define A4960_CONF1_VDS_550mV 0x0016
- #define A4960_CONF1_VDS_575mV 0x0017
- #define A4960_CONF1_VDS_600mV 0x0018
- #define A4960_CONF1_VDS_625mV 0x0019
- #define A4960_CONF1_VDS_650mV 0x001A
- #define A4960_CONF1_VDS_675mV 0x001B
- #define A4960_CONF1_VDS_700mV 0x001C
- #define A4960_CONF1_VDS_725mV 0x001D
- #define A4960_CONF1_VDS_750mV 0x001E
- #define A4960_CONF1_VDS_775mV 0x001F
- #define A4960_CONF1_VDS_800mV 0x0020
- #define A4960_CONF1_VDS_825mV 0x0021
- #define A4960_CONF1_VDS_850mV 0x0022
- #define A4960_CONF1_VDS_875mV 0x0023
- #define A4960_CONF1_VDS_900mV 0x0024
- #define A4960_CONF1_VDS_925mV 0x0025
- #define A4960_CONF1_VDS_950mV 0x0026
- #define A4960_CONF1_VDS_975mV 0x0027
- #define A4960_CONF1_VDS_1000mV 0x0028
- #define A4960_CONF1_VDS_1025mV 0x0029
- #define A4960_CONF1_VDS_1050mV 0x002A
- #define A4960_CONF1_VDS_1075mV 0x002B
- #define A4960_CONF1_VDS_1100mV 0x002C
- #define A4960_CONF1_VDS_1125mV 0x002D
- #define A4960_CONF1_VDS_1150mV 0x002E
- #define A4960_CONF1_VDS_1175mV 0x002F
- #define A4960_CONF1_VDS_1200mV 0x0030
- #define A4960_CONF1_VDS_1225mV 0x0031
- #define A4960_CONF1_VDS_1250mV 0x0032
- #define A4960_CONF1_VDS_1275mV 0x0033
- #define A4960_CONF1_VDS_1300mV 0x0034
- #define A4960_CONF1_VDS_1325mV 0x0035
- #define A4960_CONF1_VDS_1350mV 0x0036
- #define A4960_CONF1_VDS_1375mV 0x0037
- #define A4960_CONF1_VDS_1400mV 0x0038
- #define A4960_CONF1_VDS_1425mV 0x0039
- #define A4960_CONF1_VDS_1450mV 0x003A
- #define A4960_CONF1_VDS_1475mV 0x003B
- #define A4960_CONF1_VDS_1500mV 0x003C
- #define A4960_CONF1_VDS_1525mV 0x003D
- #define A4960_CONF1_VDS_1550mV 0x003E
- #define A4960_CONF1_VDS_1575mV 0x003F
- //****************************************************************************
- //end configuration-register 1
- //configuration-register 2
- //****************************************************************************
- //Bits PT[4:0]
- #define A4960_CONF2_OFFTIME_10_0us 0x0000
- #define A4960_CONF2_OFFTIME_11_6us 0x0001
- #define A4960_CONF2_OFFTIME_13_2us 0x0002
- #define A4960_CONF2_OFFTIME_14_8us 0x0003
- #define A4960_CONF2_OFFTIME_16_4us 0x0004
- #define A4960_CONF2_OFFTIME_18_0us 0x0005
- #define A4960_CONF2_OFFTIME_19_6us 0x0006
- #define A4960_CONF2_OFFTIME_21_2us 0x0007
- #define A4960_CONF2_OFFTIME_22_8us 0x0008
- #define A4960_CONF2_OFFTIME_24_4us 0x0009
- #define A4960_CONF2_OFFTIME_26_0us 0x000A
- #define A4960_CONF2_OFFTIME_27_6us 0x000B
- #define A4960_CONF2_OFFTIME_29_2us 0x000C
- #define A4960_CONF2_OFFTIME_30_8us 0x000D
- #define A4960_CONF2_OFFTIME_32_4us 0x000E
- #define A4960_CONF2_OFFTIME_34_0us 0x000F
- #define A4960_CONF2_OFFTIME_35_6us 0x0010
- #define A4960_CONF2_OFFTIME_37_2us 0x0011
- #define A4960_CONF2_OFFTIME_38_8us 0x0012
- #define A4960_CONF2_OFFTIME_40_4us 0x0013
- #define A4960_CONF2_OFFTIME_42_0us 0x0014
- #define A4960_CONF2_OFFTIME_43_6us 0x0015
- #define A4960_CONF2_OFFTIME_45_2us 0x0016
- #define A4960_CONF2_OFFTIME_46_8us 0x0017
- #define A4960_CONF2_OFFTIME_48_4us 0x0018
- #define A4960_CONF2_OFFTIME_50_0us 0x0019
- #define A4960_CONF2_OFFTIME_51_6us 0x001A
- #define A4960_CONF2_OFFTIME_53_2us 0x001B
- #define A4960_CONF2_OFFTIME_54_8us 0x001C
- #define A4960_CONF2_OFFTIME_56_4us 0x001D
- #define A4960_CONF2_OFFTIME_58_0us 0x001E
- #define A4960_CONF2_OFFTIME_59_6us 0x001F
- //****************************************************************************
- //end configuration-register 2
- //configuration-register 3
- //****************************************************************************
- //Bits IDS
- #define A4960_CONF3_CURRENT_LIMIT 0x0000
- #define A4960_CONF3_DUTYCYCLE_LIMIT 0x0100
- //Bits HQ[3:0]
- #define A4960_CONF3_STARTTORQUE_6_25per 0x0000
- #define A4960_CONF3_STARTTORQUE_12_5per 0x0010
- #define A4960_CONF3_STARTTORQUE_18_75per 0x0020
- #define A4960_CONF3_STARTTORQUE_25_0per 0x0030
- #define A4960_CONF3_STARTTORQUE_31_25per 0x0040
- #define A4960_CONF3_STARTTORQUE_37_5per 0x0050
- #define A4960_CONF3_STARTTORQUE_43_755per 0x0060
- #define A4960_CONF3_STARTTORQUE_50_0per 0x0070
- #define A4960_CONF3_STARTTORQUE_56_25per 0x0080
- #define A4960_CONF3_STARTTORQUE_62_5per 0x0090
- #define A4960_CONF3_STARTTORQUE_68_75per 0x00A0
- #define A4960_CONF3_STARTTORQUE_75_0per 0x00B0
- #define A4960_CONF3_STARTTORQUE_81_25per 0x00C0
- #define A4960_CONF3_STARTTORQUE_87_5per 0x00D0
- #define A4960_CONF3_STARTTORQUE_93_755per 0x00E0
- #define A4960_CONF3_STARTTORQUE_100_0per 0x00F0
- //Bits HT[3:0]
- #define A4960_CONF3_HOLDTIME_2ms 0x0000
- #define A4960_CONF3_HOLDTIME_10ms 0x0001
- #define A4960_CONF3_HOLDTIME_18ms 0x0002
- #define A4960_CONF3_HOLDTIME_26ms 0x0003
- #define A4960_CONF3_HOLDTIME_34ms 0x0004
- #define A4960_CONF3_HOLDTIME_42ms 0x0005
- #define A4960_CONF3_HOLDTIME_50ms 0x0006
- #define A4960_CONF3_HOLDTIME_58ms 0x0007
- #define A4960_CONF3_HOLDTIME_66ms 0x0008
- #define A4960_CONF3_HOLDTIME_74ms 0x0009
- #define A4960_CONF3_HOLDTIME_82ms 0x000A
- #define A4960_CONF3_HOLDTIME_90ms 0x000B
- #define A4960_CONF3_HOLDTIME_98ms 0x000C
- #define A4960_CONF3_HOLDTIME_106ms 0x000D
- #define A4960_CONF3_HOLDTIME_114ms 0x000E
- #define A4960_CONF3_HOLDTIME_122ms 0x000F
- //****************************************************************************
- //end configuration-register 3
- //configuration-register 4
- //****************************************************************************
- //Bits EC[3:0]
- #define A4960_CONF4_ENDCOMMUTIME_200ns 0x0000
- #define A4960_CONF4_ENDCOMMUTIME_400ns 0x0010
- #define A4960_CONF4_ENDCOMMUTIME_600ns 0x0020
- #define A4960_CONF4_ENDCOMMUTIME_800ns 0x0030
- #define A4960_CONF4_ENDCOMMUTIME_1000ns 0x0040
- #define A4960_CONF4_ENDCOMMUTIME_1200ns 0x0050
- #define A4960_CONF4_ENDCOMMUTIME_1400ns 0x0060
- #define A4960_CONF4_ENDCOMMUTIME_1600ns 0x0070
- #define A4960_CONF4_ENDCOMMUTIME_1800ns 0x0080
- #define A4960_CONF4_ENDCOMMUTIME_2000ns 0x0090
- #define A4960_CONF4_ENDCOMMUTIME_2200ns 0x00A0
- #define A4960_CONF4_ENDCOMMUTIME_2400ns 0x00B0
- #define A4960_CONF4_ENDCOMMUTIME_2600ns 0x00C0
- #define A4960_CONF4_ENDCOMMUTIME_2800ns 0x00D0
- #define A4960_CONF4_ENDCOMMUTIME_3000ns 0x00E0
- #define A4960_CONF4_ENDCOMMUTIME_3200ns 0x00F0
- //Bits SC[3:0]
- #define A4960_CONF4_STARTCOMMUTIME_8ms 0x0000
- #define A4960_CONF4_STARTCOMMUTIME_16ms 0x0001
- #define A4960_CONF4_STARTCOMMUTIME_24ms 0x0002
- #define A4960_CONF4_STARTCOMMUTIME_32ms 0x0003
- #define A4960_CONF4_STARTCOMMUTIME_40ms 0x0004
- #define A4960_CONF4_STARTCOMMUTIME_48ms 0x0005
- #define A4960_CONF4_STARTCOMMUTIME_56ms 0x0006
- #define A4960_CONF4_STARTCOMMUTIME_64ms 0x0007
- #define A4960_CONF4_STARTCOMMUTIME_72ms 0x0008
- #define A4960_CONF4_STARTCOMMUTIME_80ms 0x0009
- #define A4960_CONF4_STARTCOMMUTIME_88ms 0x000A
- #define A4960_CONF4_STARTCOMMUTIME_96ms 0x000B
- #define A4960_CONF4_STARTCOMMUTIME_104ms 0x000C
- #define A4960_CONF4_STARTCOMMUTIME_112ms 0x000D
- #define A4960_CONF4_STARTCOMMUTIME_120ms 0x000E
- #define A4960_CONF4_STARTCOMMUTIME_128ms 0x000F
- //****************************************************************************
- //end configuration-register 4
- //configuration-register 5
- //****************************************************************************
- //Bits PA[3:0]
- #define A4960_CONF5_PHASEADVANCE_0 0x0000
- #define A4960_CONF5_PHASEADVANCE_1_875 0x0100
- #define A4960_CONF5_PHASEADVANCE_3_750 0x0200
- #define A4960_CONF5_PHASEADVANCE_5_625 0x0300
- #define A4960_CONF5_PHASEADVANCE_7_500 0x0400
- #define A4960_CONF5_PHASEADVANCE_9_375 0x0500
- #define A4960_CONF5_PHASEADVANCE_11_250 0x0600
- #define A4960_CONF5_PHASEADVANCE_13_125 0x0700
- #define A4960_CONF5_PHASEADVANCE_15_000 0x0800
- #define A4960_CONF5_PHASEADVANCE_16_875 0x0900
- #define A4960_CONF5_PHASEADVANCE_18_750 0x0A00
- #define A4960_CONF5_PHASEADVANCE_20_625 0x0B00
- #define A4960_CONF5_PHASEADVANCE_22_500 0x0C00
- #define A4960_CONF5_PHASEADVANCE_24_375 0x0D00
- #define A4960_CONF5_PHASEADVANCE_26_250 0x0E00
- #define A4960_CONF5_PHASEADVANCE_28_125 0x0F00
- //Bits RQ[3:0]
- #define A4960_CONF5_RAMPTORQUE_6_25per 0x0000
- #define A4960_CONF5_RAMPTORQUE_12_5per 0x0010
- #define A4960_CONF5_RAMPTORQUE_18_75per 0x0020
- #define A4960_CONF5_RAMPTORQUE_25_0per 0x0030
- #define A4960_CONF5_RAMPTORQUE_31_25per 0x0040
- #define A4960_CONF5_RAMPTORQUE_37_5per 0x0050
- #define A4960_CONF5_RAMPTORQUE_43_755per 0x0060
- #define A4960_CONF5_RAMPTORQUE_50_0per 0x0070
- #define A4960_CONF5_RAMPTORQUE_56_25per 0x0080
- #define A4960_CONF5_RAMPTORQUE_62_5per 0x0090
- #define A4960_CONF5_RAMPTORQUE_68_75per 0x00A0
- #define A4960_CONF5_RAMPTORQUE_75_0per 0x00B0
- #define A4960_CONF5_RAMPTORQUE_81_25per 0x00C0
- #define A4960_CONF5_RAMPTORQUE_87_5per 0x00D0
- #define A4960_CONF5_RAMPTORQUE_93_755per 0x00E0
- #define A4960_CONF5_RAMPTORQUE_100_0per 0x00F0
- //Bits RR[3:0]
- #define A4960_CONF5_RAMPRATE_200ns 0x0000
- #define A4960_CONF5_RAMPRATE_400ns 0x0001
- #define A4960_CONF5_RAMPRATE_600ns 0x0002
- #define A4960_CONF5_RAMPRATE_800ns 0x0003
- #define A4960_CONF5_RAMPRATE_1000ns 0x0004
- #define A4960_CONF5_RAMPRATE_1200ns 0x0005
- #define A4960_CONF5_RAMPRATE_1400ns 0x0006
- #define A4960_CONF5_RAMPRATE_1600ns 0x0007
- #define A4960_CONF5_RAMPRATE_1800ns 0x0008
- #define A4960_CONF5_RAMPRATE_2000ns 0x0009
- #define A4960_CONF5_RAMPRATE_2200ns 0x000A
- #define A4960_CONF5_RAMPRATE_2400ns 0x000B
- #define A4960_CONF5_RAMPRATE_2600ns 0x000C
- #define A4960_CONF5_RAMPRATE_2800ns 0x000D
- #define A4960_CONF5_RAMPRATE_3000ns 0x000E
- #define A4960_CONF5_RAMPRATE_3200ns 0x000F
- //****************************************************************************
- //end configuration-register 5
- //Run-Register
- //****************************************************************************
- //Bits BH[1:0]
- #define A4960_RUN_HYSTERESIS_AUTO 0x0000
- #define A4960_RUN_HYSTERESIS_AUTO 0x0400
- #define A4960_RUN_HYSTERESIS_AUTO 0x0800
- #define A4960_RUN_HYSTERESIS_AUTO 0x0C00
- //Bits BW[2:0]
- #define A4960_RUN_BEMFWINDOW_400ns 0x0000
- #define A4960_RUN_BEMFWINDOW_800ns 0x0080
- #define A4960_RUN_BEMFWINDOW_1600ns 0x0100
- #define A4960_RUN_BEMFWINDOW_3200ns 0x0180
- #define A4960_RUN_BEMFWINDOW_6400ns 0x0200
- #define A4960_RUN_BEMFWINDOW_12800ns 0x0280
- #define A4960_RUN_BEMFWINDOW_25600ns 0x0300
- #define A4960_RUN_BEMFWINDOW_51200ns 0x0380
- //Bit ESF
- #define A4960_RUN_STOPONFAIL_ENABLE 0x0040
- #define A4960_RUN_STOPONFAIL_DISABLE 0x0000
- //Bits DG[1:0]
- #define A4960_RUN_DIAGPIN_FAULT 0x0000
- #define A4960_RUN_DIAGPIN_LOS 0x0010
- #define A4960_RUN_DIAGPIN_VDSTH 0x0020
- #define A4960_RUN_DIAGPIN_CLK 0x0030
- //Bit RSC
- #define A4960_RUN_RESTART_ENABLE 0x0008
- #define A4960_RUN_RESTART_DISABLE 0x0000
- //Bit BRK
- #define A4960_RUN_BRAKE_NORMAL 0x0000
- #define A4960_RUN_BRAKE_SLOW 0x0004
- //Bit DIR
- #define A4960_RUN_DIRECTION_FORWARD 0x0000
- #define A4960_RUN_DIRECTION_REVERSE 0x0002
- //Bit RUN
- #define A4960_RUN_RUN_COAST 0x0000
- #define A4960_RUN_RUN_START 0x0001
- //****************************************************************************
- //Mask-Register
- //****************************************************************************
- #define A4960_MASK_TEMPWARNING 0x0800
- #define A4960_MASK_THERMALSUHTDOWN 0x0400
- #define A4960_MASK_LOSSOFBEMF 0x0200
- #define A4960_MASK_BOOTCAPA 0x0100
- #define A4960_MASK_BOOTCAPB 0x0080
- #define A4960_MASK_BOOTCAPC 0x0040
- #define A4960_MASK_PHASEAHIGH 0x0020
- #define A4960_MASK_PHASEALOW 0x0010
- #define A4960_MASK_PHASEBHIGH 0x0008
- #define A4960_MASK_PHASEBLOW 0x0004
- #define A4960_MASK_PHASECHIGH 0x0002
- #define A4960_MASK_PHASECLOW 0x0001
- //****************************************************************************
- //Diagnostic-Register
- //****************************************************************************
- #define A4960_DIAG_GENERALFAULT 0x8000
- #define A4960_DIAG_POWERONRST 0x4000
- #define A4960_DIAG_UNDERVOLTAGE 0x2000
- #define A4960_DIAG_HIGHTEMP 0x0800
- #define A4960_DIAG_OVERTEMPSD 0x0400
- #define A4960_DIAG_BEMFSYNCLOST 0x0200
- #define A4960_DIAG_BOOTCAPA 0x0100
- #define A4960_DIAG_BOOTCAPB 0x0080
- #define A4960_DIAG_BOOTCAPC 0x0040
- #define A4960_DIAG_PHASEAHIGH_FAULT 0x0020
- #define A4960_DIAG_PHASEALOW_FAULT 0x0010
- #define A4960_DIAG_PHASEBHIGH_FAULT 0x0008
- #define A4960_DIAG_PHASEBLOW_FAULT 0x0004
- #define A4960_DIAG_PHASECHIGH_FAULT 0x0002
- #define A4960_DIAG_PHASEVLOW_FAULT 0x0001
- //****************************************************************************
- #endif /* A4960_H_ */
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