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| 1 | library IEEE; | |
| 2 | use IEEE.STD_LOGIC_1164.ALL; | |
| 3 | use IEEE.STD_LOGIC_ARITH.ALL; | |
| 4 | use IEEE.STD_LOGIC_UNSIGNED.ALL; | |
| 5 | -- Uncomment the following lines to use the declarations that are | |
| 6 | -- provided for instantiating Xilinx primitive components. | |
| 7 | --library UNISIM; | |
| 8 | --use UNISIM.VComponents.all; | |
| 9 | ||
| 10 | ENTITY MUX_2_1 IS | |
| 11 | PORT | |
| 12 | ( | |
| 13 | a,b,S : IN std_logic; | |
| 14 | O : OUT std_logic; | |
| 15 | ); | |
| 16 | END MUX_2_1; | |
| 17 | ||
| 18 | ARCHITECTURE Behavioral OF MUX_2_1 IS | |
| 19 | begin | |
| 20 | - | if S = '0' then |
| 20 | + | if S = '0' then |
| 21 | - | O <= a; |
| 21 | + | O <= a; |
| 22 | - | else |
| 22 | + | else |
| 23 | - | O <= b; |
| 23 | + | O <= b; |
| 24 | - | end if; |
| 24 | + | end if; |
| 25 | end Behavioral; |
