library ieee;
use ieee.std_logic_1164.all;

entity TRAFFIC_LIGHT is port
(
    CW, EV_L: in std_logic;
    Red, Yellow, Green: out std_logic;
    State: out std_logic_vector(3 downto 0)
);
end TRAFFIC_LIGHT;

architecture logic of TRAFFIC_LIGHT is
signal EV: std_logic;
begin
    EV <= EV_L;
    -- comments go here
    Green <= '1';





end logic;