Advertisement
Not a member of Pastebin yet?
Sign Up,
it unlocks many cool features!
- --------------------------------------------------------------------------------
- -- Company:
- -- Engineer:
- --
- -- Create Date: 16:08:47 09/23/2019
- -- Design Name:
- -- Module Name: C:/Users/cgtucker/CompOrg/Lab2Attempt2/full_adder_4bit_test.vhd
- -- Project Name: Lab2Attempt2
- -- Target Device:
- -- Tool versions:
- -- Description:
- --
- -- VHDL Test Bench Created by ISE for module: full_adder_4bits
- --
- -- Dependencies:
- --
- -- Revision:
- -- Revision 0.01 - File Created
- -- Additional Comments:
- --
- -- Notes:
- -- This testbench has been automatically generated using types std_logic and
- -- std_logic_vector for the ports of the unit under test. Xilinx recommends
- -- that these types always be used for the top-level I/O of a design in order
- -- to guarantee that the testbench will bind correctly to the post-implementation
- -- simulation model.
- --------------------------------------------------------------------------------
- LIBRARY ieee;
- USE ieee.std_logic_1164.ALL;
- -- Uncomment the following library declaration if using
- -- arithmetic functions with Signed or Unsigned values
- --USE ieee.numeric_std.ALL;
- ENTITY full_adder_4bit_test IS
- END full_adder_4bit_test;
- ARCHITECTURE behavior OF full_adder_4bit_test IS
- -- Component Declaration for the Unit Under Test (UUT)
- COMPONENT full_adder_4bits
- PORT(
- Cin : IN std_logic;
- A : IN std_logic_vector(3 downto 0);
- B : IN std_logic_vector(3 downto 0);
- Sout : OUT std_logic_vector(3 downto 0);
- Cout : OUT std_logic
- );
- END COMPONENT;
- --Inputs
- signal Cin : std_logic := '0';
- signal A : std_logic_vector(3 downto 0) := (others => '0');
- signal B : std_logic_vector(3 downto 0) := (others => '0');
- --Outputs
- signal Sout : std_logic_vector(3 downto 0);
- signal Cout : std_logic;
- -- No clocks detected in port list. Replace <clock> below with
- -- appropriate port name
- BEGIN
- -- Instantiate the Unit Under Test (UUT)
- uut: full_adder_4bits PORT MAP (
- Cin => Cin,
- A => A,
- B => B,
- Sout => Sout,
- Cout => Cout
- );
- -- Stimulus process
- stim_proc: process
- begin
- -- hold reset state for 100 ns.
- wait for 50 ns;
- -- insert stimulus here
- Cin <= '0';
- A <= "0001";
- B <= "0010";
- wait for 100 ns;
- Cin <= '0';
- A <= "0011";
- B <= "0100";
- wait for 100 ns;
- Cin <= '0';
- A <= "0101";
- B <= "0110";
- wait for 100 ns;
- Cin <= '0';
- A <= "0111";
- B <= "1000";
- wait for 100 ns;
- Cin <= '1';
- A <= "0001";
- B <= "0010";
- wait for 100 ns;
- Cin <= '1';
- A <= "0011";
- B <= "0100";
- wait for 100 ns;
- Cin <= '1';
- A <= "0101";
- B <= "0110";
- wait for 100 ns;
- Cin <= '1';
- A <= "0111";
- B <= "1000";
- wait for 100 ns;
- wait;
- end process;
- END;
Advertisement
Add Comment
Please, Sign In to add comment
Advertisement