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Oct 15th, 2020
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VHDL 0.76 KB | None | 0 0
  1. LIBRARY IEEE;
  2. USE IEEE.std_logic_1164.ALL;
  3. USE IEEE.numeric_std.ALL;
  4. -- Generates 16 ticks per bit
  5. ENTITY baud_gen IS
  6.   GENERIC(divider: INTEGER := 13 -- 24M/115200*16
  7.           );
  8.   PORT(
  9.     clk, reset: IN STD_LOGIC;
  10.     s_tick: OUT STD_LOGIC
  11.     );
  12. END baud_gen;
  13.  
  14. ARCHITECTURE working OF baud_gen IS
  15.  
  16. BEGIN
  17.   PROCESS(clk)
  18.     VARIABLE counter: UNSIGNED(3 DOWNTO 0) := to_unsigned(0,4);
  19.   BEGIN
  20.     IF clk'EVENT AND clk='1' THEN
  21.       IF reset='1' THEN
  22.         s_tick <= '0';
  23.         counter := to_unsigned(0,4);
  24.       ELSIF counter=to_unsigned(divider-1,4) then
  25.         s_tick <= '1';
  26.         counter:= to_unsigned(0,4);
  27.       ELSE
  28.         s_tick <= '0';
  29.         counter := counter + 1;
  30.       END IF;
  31.     END IF;
  32.   END PROCESS;
  33. END working;
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