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  1. /dts-v1/;
  2.  
  3. / {
  4. #address-cells = <0x01>;
  5. #size-cells = <0x01>;
  6. compatible = "friendlyarm,nanopi-neo-air\0allwinner,sun8i-h3";
  7. interrupt-parent = <0x01>;
  8. model = "FriendlyARM NanoPi NEO Air";
  9. serial-number = "02c00081cf897191";
  10.  
  11. __symbols__ {
  12. brcmf = "/soc/mmc@1c10000/bcrmf@1";
  13. bt_pwr_pin = "/soc/pinctrl@1c20800/bt_pwr_pin@0";
  14. cam_xclk = "/cam-xclk";
  15. ccu = "/soc/clock@1c20000";
  16. codec = "/soc/codec@1c22c00";
  17. codec_analog = "/soc/codec-analog@1f015c0";
  18. cpu0 = "/cpus/cpu@0";
  19. cpu0_opp_table = "/opp-table-cpu";
  20. cpu1 = "/cpus/cpu@1";
  21. cpu2 = "/cpus/cpu@2";
  22. cpu3 = "/cpus/cpu@3";
  23. cpu_crit = "/thermal-zones/cpu_thermal/trips/cpu_crit";
  24. cpu_hot = "/thermal-zones/cpu_thermal/trips/cpu_hot";
  25. cpu_hot_pre = "/thermal-zones/cpu_thermal/trips/cpu_hot_pre";
  26. cpu_very_hot = "/thermal-zones/cpu_thermal/trips/cpu_very_hot";
  27. cpu_very_hot_pre = "/thermal-zones/cpu_thermal/trips/cpu_very_hot_pre";
  28. cpu_warm = "/thermal-zones/cpu_thermal/trips/cpu_warm";
  29. crypto = "/soc/crypto@1c15000";
  30. csi = "/soc/camera@1cb0000";
  31. csi_from_ov5640 = "/soc/camera@1cb0000/port/endpoint";
  32. csi_pins = "/soc/pinctrl@1c20800/csi-pins";
  33. de = "/display-engine";
  34. deinterlace = "/soc/deinterlace@1400000";
  35. display_clocks = "/soc/clock@1000000";
  36. dma = "/soc/dma-controller@1c02000";
  37. ehci0 = "/soc/usb@1c1a000";
  38. ehci1 = "/soc/usb@1c1b000";
  39. ehci2 = "/soc/usb@1c1c000";
  40. ehci3 = "/soc/usb@1c1d000";
  41. emac = "/soc/ethernet@1c30000";
  42. emac_rgmii_pins = "/soc/pinctrl@1c20800/emac-rgmii-pins";
  43. external_mdio = "/soc/ethernet@1c30000/mdio-mux/mdio@2";
  44. gic = "/soc/interrupt-controller@1c81000";
  45. gpu_opp_table = "/opp-table-gpu";
  46. hdmi = "/soc/hdmi@1ee0000";
  47. hdmi_in = "/soc/hdmi@1ee0000/ports/port@0";
  48. hdmi_in_tcon0 = "/soc/hdmi@1ee0000/ports/port@0/endpoint";
  49. hdmi_out = "/soc/hdmi@1ee0000/ports/port@1";
  50. hdmi_phy = "/soc/hdmi-phy@1ef0000";
  51. i2c0 = "/soc/i2c@1c2ac00";
  52. i2c0_pins = "/soc/pinctrl@1c20800/i2c0-pins";
  53. i2c1 = "/soc/i2c@1c2b000";
  54. i2c1_pins = "/soc/pinctrl@1c20800/i2c1-pins";
  55. i2c2 = "/soc/i2c@1c2b400";
  56. i2c2_pins = "/soc/pinctrl@1c20800/i2c2-pins";
  57. i2s0 = "/soc/i2s@1c22000";
  58. i2s0_pins = "/soc/pinctrl@1c20800/i2s0-pins";
  59. i2s1 = "/soc/i2s@1c22400";
  60. i2s1_pins = "/soc/pinctrl@1c20800/i2s1-pins";
  61. i2s2 = "/soc/i2s@1c22800";
  62. int_mii_phy = "/soc/ethernet@1c30000/mdio-mux/mdio@1/ethernet-phy@1";
  63. internal_mdio = "/soc/ethernet@1c30000/mdio-mux/mdio@1";
  64. ir = "/soc/ir@1f02000";
  65. mali = "/soc/gpu@1c40000";
  66. mbus = "/soc/dram-controller@1c62000";
  67. mdio = "/soc/ethernet@1c30000/mdio";
  68. mixer0 = "/soc/mixer@1100000";
  69. mixer0_out = "/soc/mixer@1100000/ports/port@1";
  70. mixer0_out_tcon0 = "/soc/mixer@1100000/ports/port@1/endpoint";
  71. mmc0 = "/soc/mmc@1c0f000";
  72. mmc0_pins = "/soc/pinctrl@1c20800/mmc0-pins";
  73. mmc1 = "/soc/mmc@1c10000";
  74. mmc1_pins = "/soc/pinctrl@1c20800/mmc1-pins";
  75. mmc2 = "/soc/mmc@1c11000";
  76. mmc2_8bit_pins = "/soc/pinctrl@1c20800/mmc2-8bit-pins";
  77. msgbox = "/soc/mailbox@1c17000";
  78. ohci0 = "/soc/usb@1c1a400";
  79. ohci1 = "/soc/usb@1c1b400";
  80. ohci2 = "/soc/usb@1c1c400";
  81. ohci3 = "/soc/usb@1c1d400";
  82. osc24M = "/clocks/osc24M_clk";
  83. osc32k = "/clocks/osc32k_clk";
  84. ov5640 = "/soc/i2c@1c2b400/camera@3c";
  85. ov5640_to_csi = "/soc/i2c@1c2b400/camera@3c/port/endpoint";
  86. pio = "/soc/pinctrl@1c20800";
  87. pull_pins = "/soc/pinctrl@1c20800/pull_pins";
  88. pwm = "/soc/pwm@1c21400";
  89. r_ccu = "/soc/clock@1f01400";
  90. r_i2c = "/soc/i2c@1f02400";
  91. r_i2c_pins = "/soc/pinctrl@1f02c00/r-i2c-pins";
  92. r_intc = "/soc/interrupt-controller@1f00c00";
  93. r_ir_rx_pin = "/soc/pinctrl@1f02c00/r-ir-rx-pin";
  94. r_pio = "/soc/pinctrl@1f02c00";
  95. r_pwm = "/soc/pwm@1f03800";
  96. r_pwm_pin = "/soc/pinctrl@1f02c00/r-pwm-pin";
  97. reg_ahci_5v = "/ahci-5v";
  98. reg_cam_avdd = "/cam-avdd";
  99. reg_cam_dovdd = "/cam-dovdd";
  100. reg_cam_dvdd = "/cam-dvdd";
  101. reg_usb0_vbus = "/usb0-vbus";
  102. reg_usb1_vbus = "/usb1-vbus";
  103. reg_usb2_vbus = "/usb2-vbus";
  104. reg_vcc3v0 = "/vcc3v0";
  105. reg_vcc3v3 = "/vcc3v3";
  106. reg_vcc5v0 = "/vcc5v0";
  107. rtc = "/soc/rtc@1f00000";
  108. scpi_protocol = "/scpi";
  109. scpi_sram = "/soc/system-control@1c00000/sram@40000/scp-shmem@bc00";
  110. sid = "/soc/eeprom@1c14000";
  111. sound_hdmi = "/sound_hdmi";
  112. spdif = "/soc/spdif@1c21000";
  113. spdif_tx_pin = "/soc/pinctrl@1c20800/spdif-tx-pin";
  114. spi0 = "/soc/spi@1c68000";
  115. spi0_pins = "/soc/pinctrl@1c20800/spi0-pins";
  116. spi1 = "/soc/spi@1c69000";
  117. spi1_pins = "/soc/pinctrl@1c20800/spi1-pins";
  118. sram_a2 = "/soc/system-control@1c00000/sram@40000";
  119. sram_c = "/soc/system-control@1c00000/sram@1d00000";
  120. st7789 = "/soc/spi@1c68000/st7789@0";
  121. syscon = "/soc/system-control@1c00000";
  122. tcon0 = "/soc/lcd-controller@1c0c000";
  123. tcon0_in = "/soc/lcd-controller@1c0c000/ports/port@0";
  124. tcon0_in_mixer0 = "/soc/lcd-controller@1c0c000/ports/port@0/endpoint";
  125. tcon0_out = "/soc/lcd-controller@1c0c000/ports/port@1";
  126. tcon0_out_hdmi = "/soc/lcd-controller@1c0c000/ports/port@1/endpoint@1";
  127. ths = "/soc/thermal-sensor@1c25000";
  128. ths_calibration = "/soc/eeprom@1c14000/thermal-sensor-calibration@34";
  129. uart0 = "/soc/serial@1c28000";
  130. uart0_pa_pins = "/soc/pinctrl@1c20800/uart0-pa-pins";
  131. uart1 = "/soc/serial@1c28400";
  132. uart1_pins = "/soc/pinctrl@1c20800/uart1-pins";
  133. uart1_rts_cts_pins = "/soc/pinctrl@1c20800/uart1-rts-cts-pins";
  134. uart2 = "/soc/serial@1c28800";
  135. uart2_pins = "/soc/pinctrl@1c20800/uart2-pins";
  136. uart2_rts_cts_pins = "/soc/pinctrl@1c20800/uart2-rts-cts-pins";
  137. uart3 = "/soc/serial@1c28c00";
  138. uart3_pins = "/soc/pinctrl@1c20800/uart3-pins";
  139. uart3_rts_cts_pins = "/soc/pinctrl@1c20800/uart3-rts-cts-pins";
  140. usb_otg = "/soc/usb@1c19000";
  141. usbphy = "/soc/phy@1c19400";
  142. vdd_cpux = "/gpio-regulator";
  143. ve_sram = "/soc/system-control@1c00000/sram@1d00000/sram-section@0";
  144. wdt0 = "/soc/watchdog@1c20ca0";
  145. wifi_en_npi = "/soc/pinctrl@1f02c00/wifi_en_pin";
  146. wifi_pwrseq = "/wifi_pwrseq";
  147. };
  148.  
  149. ahci-5v {
  150. compatible = "regulator-fixed";
  151. enable-active-high;
  152. gpio = <0x0e 0x01 0x08 0x00>;
  153. phandle = <0x80>;
  154. regulator-boot-on;
  155. regulator-max-microvolt = <0x4c4b40>;
  156. regulator-min-microvolt = <0x4c4b40>;
  157. regulator-name = "ahci-5v";
  158. status = "disabled";
  159. };
  160.  
  161. aliases {
  162. mmc0 = "/soc/mmc@1c0f000";
  163. mmc1 = "/soc/mmc@1c10000";
  164. mmc2 = "/soc/mmc@1c11000";
  165. serial0 = "/soc/serial@1c28000";
  166. };
  167.  
  168. cam-avdd {
  169. compatible = "regulator-fixed";
  170. phandle = <0x23>;
  171. regulator-max-microvolt = <0x2ab980>;
  172. regulator-min-microvolt = <0x2ab980>;
  173. regulator-name = "cam500b-avdd";
  174. vin-supply = <0x0d>;
  175. };
  176.  
  177. cam-dovdd {
  178. compatible = "regulator-fixed";
  179. phandle = <0x24>;
  180. regulator-max-microvolt = <0x1b7740>;
  181. regulator-min-microvolt = <0x1b7740>;
  182. regulator-name = "cam500b-dovdd";
  183. vin-supply = <0x0d>;
  184. };
  185.  
  186. cam-dvdd {
  187. compatible = "regulator-fixed";
  188. phandle = <0x25>;
  189. regulator-max-microvolt = <0x16e360>;
  190. regulator-min-microvolt = <0x16e360>;
  191. regulator-name = "cam500b-dvdd";
  192. vin-supply = <0x0d>;
  193. };
  194.  
  195. cam-xclk {
  196. #clock-cells = <0x00>;
  197. clock-frequency = <0x16e3600>;
  198. clock-output-names = "cam-xclk";
  199. compatible = "fixed-clock";
  200. phandle = <0x22>;
  201. };
  202.  
  203. chosen {
  204. #address-cells = <0x01>;
  205. #size-cells = <0x01>;
  206. bootargs = "root=UUID=67672fac-b6bc-49c5-9c07-cf4480586a04 rootwait rootfstype=ext4 splash=verbose console=ttyS0,115200 hdmi.audio=EDID:0 disp.screen0_output_mode=1920x1080p60 consoleblank=0 loglevel=1 ubootpart=5ec7151c-01 ubootsource=mmc usb-storage.quirks=0x2537:0x1066:u,0x2537:0x1068:u fbcon=map:1 sunxi_ve_mem_reserve=0 sunxi_g2d_mem_reserve=0 sunxi_fb_mem_reserve=16 cgroup_enable=memory swapaccount=1";
  207. linux,initrd-end = <0x49fff372>;
  208. linux,initrd-start = <0x497b9000>;
  209. ranges;
  210. stdout-path = "serial0:115200n8";
  211. u-boot,version = "2022.07-armbian";
  212.  
  213. framebuffer-hdmi {
  214. allwinner,pipeline = "mixer0-lcd0-hdmi";
  215. clocks = <0x02 0x06 0x03 0x66 0x03 0x6f>;
  216. compatible = "allwinner,simple-framebuffer\0simple-framebuffer";
  217. status = "disabled";
  218. };
  219.  
  220. framebuffer-tve {
  221. allwinner,pipeline = "mixer1-lcd1-tve";
  222. clocks = <0x02 0x07 0x03 0x67>;
  223. compatible = "allwinner,simple-framebuffer\0simple-framebuffer";
  224. status = "disabled";
  225. };
  226. };
  227.  
  228. clocks {
  229. #address-cells = <0x01>;
  230. #size-cells = <0x01>;
  231. ranges;
  232.  
  233. osc24M_clk {
  234. #clock-cells = <0x00>;
  235. clock-accuracy = <0xc350>;
  236. clock-frequency = <0x16e3600>;
  237. clock-output-names = "osc24M";
  238. compatible = "fixed-clock";
  239. phandle = <0x13>;
  240. };
  241.  
  242. osc32k_clk {
  243. #clock-cells = <0x00>;
  244. clock-accuracy = <0xc350>;
  245. clock-frequency = <0x8000>;
  246. clock-output-names = "ext_osc32k";
  247. compatible = "fixed-clock";
  248. phandle = <0x2b>;
  249. };
  250. };
  251.  
  252. cpus {
  253. #address-cells = <0x01>;
  254. #size-cells = <0x00>;
  255.  
  256. cpu@0 {
  257. #cooling-cells = <0x02>;
  258. clock-names = "cpu";
  259. clocks = <0x03 0x0e>;
  260. compatible = "arm,cortex-a7";
  261. cpu-supply = <0x34>;
  262. device_type = "cpu";
  263. enable-method = "psci";
  264. operating-points-v2 = <0x33>;
  265. phandle = <0x35>;
  266. reg = <0x00>;
  267. };
  268.  
  269. cpu@1 {
  270. #cooling-cells = <0x02>;
  271. clock-names = "cpu";
  272. clocks = <0x03 0x0e>;
  273. compatible = "arm,cortex-a7";
  274. device_type = "cpu";
  275. enable-method = "psci";
  276. operating-points-v2 = <0x33>;
  277. phandle = <0x36>;
  278. reg = <0x01>;
  279. };
  280.  
  281. cpu@2 {
  282. #cooling-cells = <0x02>;
  283. clock-names = "cpu";
  284. clocks = <0x03 0x0e>;
  285. compatible = "arm,cortex-a7";
  286. device_type = "cpu";
  287. enable-method = "psci";
  288. operating-points-v2 = <0x33>;
  289. phandle = <0x37>;
  290. reg = <0x02>;
  291. };
  292.  
  293. cpu@3 {
  294. #cooling-cells = <0x02>;
  295. clock-names = "cpu";
  296. clocks = <0x03 0x0e>;
  297. compatible = "arm,cortex-a7";
  298. device_type = "cpu";
  299. enable-method = "psci";
  300. operating-points-v2 = <0x33>;
  301. phandle = <0x38>;
  302. reg = <0x03>;
  303. };
  304. };
  305.  
  306. display-engine {
  307. allwinner,pipelines = <0x04>;
  308. compatible = "allwinner,sun8i-h3-display-engine";
  309. phandle = <0x42>;
  310. status = "disabled";
  311. };
  312.  
  313. gpio-regulator {
  314. compatible = "regulator-gpio";
  315. gpios = <0x3f 0x00 0x06 0x00>;
  316. gpios-states = <0x01>;
  317. phandle = <0x34>;
  318. pinctrl-names = "default";
  319. regulator-always-on;
  320. regulator-boot-on;
  321. regulator-max-microvolt = <0x13d620>;
  322. regulator-min-microvolt = <0x10c8e0>;
  323. regulator-name = "vdd-cpux";
  324. regulator-ramp-delay = <0x32>;
  325. regulator-type = "voltage";
  326. states = <0x10c8e0 0x00 0x13d620 0x01>;
  327. };
  328.  
  329. leds {
  330. compatible = "gpio-leds";
  331.  
  332. led-0 {
  333. default-state = "on";
  334. gpios = <0x3f 0x00 0x0a 0x00>;
  335. label = "nanopi:green:pwr";
  336. };
  337.  
  338. led-1 {
  339. gpios = <0x0e 0x00 0x0a 0x00>;
  340. label = "nanopi:blue:status";
  341. linux,default-trigger = "heartbeat";
  342. };
  343. };
  344.  
  345. memory {
  346. device_type = "memory";
  347. reg = <0x40000000 0x20000000>;
  348. };
  349.  
  350. opp-table-cpu {
  351. compatible = "operating-points-v2";
  352. opp-shared;
  353. phandle = <0x33>;
  354.  
  355. opp-1008000000 {
  356. clock-latency-ns = <0x3b9b0>;
  357. opp-hz = <0x00 0x3c14dc00>;
  358. opp-microvolt = <0x124f80 0x124f80 0x13d620>;
  359. };
  360.  
  361. opp-1104000000 {
  362. clock-latency-ns = <0x3b9b0>;
  363. opp-hz = <0x00 0x41cdb400>;
  364. opp-microvolt = <0x142440 0x142440 0x142440>;
  365. };
  366.  
  367. opp-1200000000 {
  368. clock-latency-ns = <0x3b9b0>;
  369. opp-hz = <0x00 0x47868c00>;
  370. opp-microvolt = <0x142440 0x142440 0x142440>;
  371. };
  372.  
  373. opp-1296000000 {
  374. clock-latency-ns = <0x3b9b0>;
  375. opp-hz = <0x00 0x4d3f6400>;
  376. opp-microvolt = <0x147260 0x147260 0x147260>;
  377. };
  378.  
  379. opp-1368000000 {
  380. clock-latency-ns = <0x3b9b0>;
  381. opp-hz = <0x00 0x518a0600>;
  382. opp-microvolt = <0x155cc0 0x155cc0 0x155cc0>;
  383. };
  384.  
  385. opp-480000000 {
  386. clock-latency-ns = <0x3b9b0>;
  387. opp-hz = <0x00 0x1c9c3800>;
  388. opp-microvolt = <0xfde80 0xfde80 0x13d620>;
  389. };
  390.  
  391. opp-648000000 {
  392. clock-latency-ns = <0x3b9b0>;
  393. opp-hz = <0x00 0x269fb200>;
  394. opp-microvolt = <0xfde80 0xfde80 0x13d620>;
  395. };
  396.  
  397. opp-816000000 {
  398. clock-latency-ns = <0x3b9b0>;
  399. opp-hz = <0x00 0x30a32c00>;
  400. opp-microvolt = <0x10c8e0 0x10c8e0 0x13d620>;
  401. };
  402.  
  403. opp-960000000 {
  404. clock-latency-ns = <0x3b9b0>;
  405. opp-hz = <0x00 0x39387000>;
  406. opp-microvolt = <0x124f80 0x124f80 0x13d620>;
  407. };
  408. };
  409.  
  410. opp-table-gpu {
  411. compatible = "operating-points-v2";
  412. phandle = <0x31>;
  413.  
  414. opp-120000000 {
  415. opp-hz = <0x00 0x7270e00>;
  416. };
  417.  
  418. opp-312000000 {
  419. opp-hz = <0x00 0x1298be00>;
  420. };
  421.  
  422. opp-432000000 {
  423. opp-hz = <0x00 0x19bfcc00>;
  424. };
  425.  
  426. opp-576000000 {
  427. opp-hz = <0x00 0x22551000>;
  428. };
  429. };
  430.  
  431. pmu {
  432. compatible = "arm,cortex-a7-pmu";
  433. interrupt-affinity = <0x35 0x36 0x37 0x38>;
  434. interrupts = <0x00 0x78 0x04 0x00 0x79 0x04 0x00 0x7a 0x04 0x00 0x7b 0x04>;
  435. };
  436.  
  437. psci {
  438. compatible = "arm,psci";
  439. cpu_off = <0x95c1ba5f>;
  440. cpu_on = <0x95c1ba60>;
  441. cpu_suspend = <0x95c1ba5e>;
  442. method = "smc";
  443. migrate = <0x95c1ba61>;
  444. status = "okay";
  445. };
  446.  
  447. rfkill_bt {
  448. clock-frequency = <0x8000>;
  449. clocks = <0x2b>;
  450. compatible = "rfkill-gpio";
  451. pinctrl-0 = <0x41>;
  452. pinctrl-names = "default";
  453. reset-gpios = <0x0e 0x06 0x0d 0x00>;
  454. rfkill-name = "sunxi-bt";
  455. rfkill-type = "bluetooth";
  456. };
  457.  
  458. scpi {
  459. compatible = "arm,scpi";
  460. mbox-names = "tx\0rx";
  461. mboxes = <0x07 0x02 0x07 0x03>;
  462. phandle = <0x44>;
  463. shmem = <0x08>;
  464. };
  465.  
  466. soc {
  467. #address-cells = <0x01>;
  468. #size-cells = <0x01>;
  469. compatible = "simple-bus";
  470. dma-ranges;
  471. ranges;
  472.  
  473. camera@1cb0000 {
  474. clock-names = "bus\0mod\0ram";
  475. clocks = <0x03 0x2d 0x03 0x6a 0x03 0x62>;
  476. compatible = "allwinner,sun8i-h3-csi";
  477. interrupts = <0x00 0x54 0x04>;
  478. phandle = <0x73>;
  479. pinctrl-0 = <0x27>;
  480. pinctrl-names = "default";
  481. reg = <0x1cb0000 0x1000>;
  482. resets = <0x03 0x1e>;
  483. status = "okay";
  484.  
  485. port {
  486. #address-cells = <0x01>;
  487. #size-cells = <0x00>;
  488.  
  489. endpoint {
  490. bus-width = <0x08>;
  491. data-active = <0x01>;
  492. data-shift = <0x02>;
  493. hsync-active = <0x01>;
  494. pclk-sample = <0x01>;
  495. phandle = <0x26>;
  496. remote-endpoint = <0x28>;
  497. vsync-active = <0x00>;
  498. };
  499. };
  500. };
  501.  
  502. clock@1000000 {
  503. #clock-cells = <0x01>;
  504. #reset-cells = <0x01>;
  505. clock-names = "bus\0mod";
  506. clocks = <0x03 0x30 0x03 0x65>;
  507. compatible = "allwinner,sun8i-h3-de2-clk";
  508. phandle = <0x02>;
  509. reg = <0x1000000 0x10000>;
  510. resets = <0x03 0x22>;
  511. };
  512.  
  513. clock@1c20000 {
  514. #clock-cells = <0x01>;
  515. #reset-cells = <0x01>;
  516. clock-names = "hosc\0losc";
  517. clocks = <0x13 0x14 0x00>;
  518. compatible = "allwinner,sun8i-h3-ccu";
  519. phandle = <0x03>;
  520. protected-clocks = <0x32>;
  521. reg = <0x1c20000 0x400>;
  522. };
  523.  
  524. clock@1f01400 {
  525. #clock-cells = <0x01>;
  526. #reset-cells = <0x01>;
  527. clock-names = "hosc\0losc\0iosc\0pll-periph";
  528. clocks = <0x13 0x14 0x00 0x14 0x02 0x03 0x09>;
  529. compatible = "allwinner,sun8i-h3-r-ccu";
  530. phandle = <0x2c>;
  531. protected-clocks = <0x0a>;
  532. reg = <0x1f01400 0x100>;
  533. };
  534.  
  535. codec-analog@1f015c0 {
  536. compatible = "allwinner,sun8i-h3-codec-analog";
  537. phandle = <0x1b>;
  538. reg = <0x1f015c0 0x04>;
  539. };
  540.  
  541. codec@1c22c00 {
  542. #sound-dai-cells = <0x00>;
  543. allwinner,codec-analog-controls = <0x1b>;
  544. clock-names = "apb\0codec";
  545. clocks = <0x03 0x34 0x03 0x6d>;
  546. compatible = "allwinner,sun8i-h3-codec";
  547. dma-names = "rx\0tx";
  548. dmas = <0x18 0x0f 0x18 0x0f>;
  549. interrupts = <0x00 0x1d 0x04>;
  550. phandle = <0x6a>;
  551. reg = <0x1c22c00 0x400>;
  552. resets = <0x03 0x28>;
  553. status = "disabled";
  554. };
  555.  
  556. crypto@1c15000 {
  557. clock-names = "bus\0mod";
  558. clocks = <0x03 0x14 0x03 0x51>;
  559. compatible = "allwinner,sun8i-h3-crypto";
  560. interrupts = <0x00 0x5e 0x04>;
  561. phandle = <0x7d>;
  562. reg = <0x1c15000 0x1000>;
  563. resets = <0x03 0x05>;
  564. };
  565.  
  566. deinterlace@1400000 {
  567. clock-names = "bus\0mod\0ram";
  568. clocks = <0x03 0x2c 0x03 0x68 0x03 0x63>;
  569. compatible = "allwinner,sun8i-h3-deinterlace";
  570. interconnect-names = "dma-mem";
  571. interconnects = <0x2f 0x09>;
  572. interrupts = <0x00 0x5d 0x04>;
  573. phandle = <0x7a>;
  574. reg = <0x1400000 0x20000>;
  575. resets = <0x03 0x1d>;
  576. };
  577.  
  578. dma-controller@1c02000 {
  579. #dma-cells = <0x01>;
  580. clocks = <0x03 0x15>;
  581. compatible = "allwinner,sun8i-h3-dma";
  582. interrupts = <0x00 0x32 0x04>;
  583. phandle = <0x18>;
  584. reg = <0x1c02000 0x1000>;
  585. resets = <0x03 0x06>;
  586. };
  587.  
  588. dram-controller@1c62000 {
  589. #address-cells = <0x01>;
  590. #interconnect-cells = <0x01>;
  591. #size-cells = <0x01>;
  592. clock-names = "apb\0dram\0mbus";
  593. clocks = <0x03 0x1a 0x03 0x60 0x03 0x71>;
  594. compatible = "allwinner,sun8i-h3-mbus";
  595. dma-ranges = <0x00 0x40000000 0xc0000000>;
  596. phandle = <0x2f>;
  597. reg = <0x1c62000 0x1000 0x1c63000 0x1000>;
  598. reg-names = "mbus\0dram";
  599. };
  600.  
  601. eeprom@1c14000 {
  602. #address-cells = <0x01>;
  603. #size-cells = <0x01>;
  604. compatible = "allwinner,sun8i-h3-sid";
  605. phandle = <0x4d>;
  606. reg = <0x1c14000 0x400>;
  607.  
  608. thermal-sensor-calibration@34 {
  609. phandle = <0x32>;
  610. reg = <0x34 0x04>;
  611. };
  612. };
  613.  
  614. ethernet@1c30000 {
  615. clock-names = "stmmaceth";
  616. clocks = <0x03 0x1b>;
  617. compatible = "allwinner,sun8i-h3-emac";
  618. interrupt-names = "macirq";
  619. interrupts = <0x00 0x52 0x04>;
  620. phandle = <0x5f>;
  621. reg = <0x1c30000 0x10000>;
  622. reset-names = "stmmaceth";
  623. resets = <0x03 0x0c>;
  624. status = "disabled";
  625. syscon = <0x16>;
  626.  
  627. mdio {
  628. #address-cells = <0x01>;
  629. #size-cells = <0x00>;
  630. compatible = "snps,dwmac-mdio";
  631. phandle = <0x17>;
  632. };
  633.  
  634. mdio-mux {
  635. #address-cells = <0x01>;
  636. #size-cells = <0x00>;
  637. compatible = "allwinner,sun8i-h3-mdio-mux";
  638. mdio-parent-bus = <0x17>;
  639.  
  640. mdio@1 {
  641. #address-cells = <0x01>;
  642. #size-cells = <0x00>;
  643. compatible = "allwinner,sun8i-h3-mdio-internal";
  644. phandle = <0x60>;
  645. reg = <0x01>;
  646.  
  647. ethernet-phy@1 {
  648. clocks = <0x03 0x43>;
  649. compatible = "ethernet-phy-ieee802.3-c22";
  650. phandle = <0x61>;
  651. reg = <0x01>;
  652. resets = <0x03 0x27>;
  653. };
  654. };
  655.  
  656. mdio@2 {
  657. #address-cells = <0x01>;
  658. #size-cells = <0x00>;
  659. phandle = <0x62>;
  660. reg = <0x02>;
  661. };
  662. };
  663. };
  664.  
  665. gpu@1c40000 {
  666. clock-names = "bus\0core";
  667. clocks = <0x03 0x31 0x03 0x72>;
  668. compatible = "allwinner,sun8i-h3-mali\0arm,mali-400";
  669. interrupt-names = "gp\0gpmmu\0pp0\0ppmmu0\0pp1\0ppmmu1\0pmu";
  670. interrupts = <0x00 0x61 0x04 0x00 0x62 0x04 0x00 0x63 0x04 0x00 0x64 0x04 0x00 0x66 0x04 0x00 0x67 0x04 0x00 0x65 0x04>;
  671. operating-points-v2 = <0x31>;
  672. phandle = <0x7e>;
  673. reg = <0x1c40000 0x10000>;
  674. resets = <0x03 0x23>;
  675. };
  676.  
  677. hdmi-phy@1ef0000 {
  678. #phy-cells = <0x00>;
  679. clock-names = "bus\0mod\0pll-0";
  680. clocks = <0x03 0x2f 0x03 0x70 0x03 0x06>;
  681. compatible = "allwinner,sun8i-h3-hdmi-phy";
  682. phandle = <0x29>;
  683. reg = <0x1ef0000 0x10000>;
  684. reset-names = "phy";
  685. resets = <0x03 0x20>;
  686. };
  687.  
  688. hdmi@1ee0000 {
  689. #sound-dai-cells = <0x00>;
  690. clock-names = "iahb\0isfr\0tmds";
  691. clocks = <0x03 0x2f 0x03 0x70 0x03 0x6f>;
  692. compatible = "allwinner,sun8i-h3-dw-hdmi\0allwinner,sun8i-a83t-dw-hdmi";
  693. interrupts = <0x00 0x58 0x04>;
  694. phandle = <0x05>;
  695. phy-names = "phy";
  696. phys = <0x29>;
  697. reg = <0x1ee0000 0x10000>;
  698. reg-io-width = <0x01>;
  699. reset-names = "ctrl";
  700. resets = <0x03 0x21>;
  701. status = "disabled";
  702.  
  703. ports {
  704. #address-cells = <0x01>;
  705. #size-cells = <0x00>;
  706.  
  707. port@0 {
  708. phandle = <0x74>;
  709. reg = <0x00>;
  710.  
  711. endpoint {
  712. phandle = <0x0b>;
  713. remote-endpoint = <0x2a>;
  714. };
  715. };
  716.  
  717. port@1 {
  718. phandle = <0x75>;
  719. reg = <0x01>;
  720. };
  721. };
  722. };
  723.  
  724. i2c@1c2ac00 {
  725. #address-cells = <0x01>;
  726. #size-cells = <0x00>;
  727. clocks = <0x03 0x3b>;
  728. compatible = "allwinner,sun6i-a31-i2c";
  729. interrupts = <0x00 0x06 0x04>;
  730. phandle = <0x6f>;
  731. pinctrl-0 = <0x1f>;
  732. pinctrl-names = "default";
  733. reg = <0x1c2ac00 0x400>;
  734. resets = <0x03 0x2e>;
  735. status = "disabled";
  736. };
  737.  
  738. i2c@1c2b000 {
  739. #address-cells = <0x01>;
  740. #size-cells = <0x00>;
  741. clocks = <0x03 0x3c>;
  742. compatible = "allwinner,sun6i-a31-i2c";
  743. interrupts = <0x00 0x07 0x04>;
  744. phandle = <0x70>;
  745. pinctrl-0 = <0x20>;
  746. pinctrl-names = "default";
  747. reg = <0x1c2b000 0x400>;
  748. resets = <0x03 0x2f>;
  749. status = "disabled";
  750. };
  751.  
  752. i2c@1c2b400 {
  753. #address-cells = <0x01>;
  754. #size-cells = <0x00>;
  755. clocks = <0x03 0x3d>;
  756. compatible = "allwinner,sun6i-a31-i2c";
  757. interrupts = <0x00 0x08 0x04>;
  758. phandle = <0x71>;
  759. pinctrl-0 = <0x21>;
  760. pinctrl-names = "default";
  761. reg = <0x1c2b400 0x400>;
  762. resets = <0x03 0x30>;
  763. status = "okay";
  764.  
  765. camera@3c {
  766. AVDD-supply = <0x23>;
  767. DOVDD-supply = <0x24>;
  768. DVDD-supply = <0x25>;
  769. clock-names = "xclk";
  770. clocks = <0x22>;
  771. compatible = "ovti,ov5640";
  772. phandle = <0x72>;
  773. powerdown-gpios = <0x0e 0x04 0x0f 0x00>;
  774. reg = <0x3c>;
  775. reset-gpios = <0x0e 0x04 0x0e 0x01>;
  776.  
  777. port {
  778.  
  779. endpoint {
  780. bus-width = <0x08>;
  781. data-active = <0x01>;
  782. data-shift = <0x02>;
  783. hsync-active = <0x01>;
  784. pclk-sample = <0x01>;
  785. phandle = <0x28>;
  786. remote-endpoint = <0x26>;
  787. vsync-active = <0x00>;
  788. };
  789. };
  790. };
  791. };
  792.  
  793. i2c@1f02400 {
  794. #address-cells = <0x01>;
  795. #size-cells = <0x00>;
  796. clocks = <0x2c 0x09>;
  797. compatible = "allwinner,sun6i-a31-i2c";
  798. interrupts = <0x00 0x2c 0x04>;
  799. phandle = <0x77>;
  800. pinctrl-0 = <0x2d>;
  801. pinctrl-names = "default";
  802. reg = <0x1f02400 0x400>;
  803. resets = <0x2c 0x05>;
  804. status = "disabled";
  805. };
  806.  
  807. i2s@1c22000 {
  808. #sound-dai-cells = <0x00>;
  809. clock-names = "apb\0mod";
  810. clocks = <0x03 0x38 0x03 0x54>;
  811. compatible = "allwinner,sun8i-h3-i2s";
  812. dma-names = "rx\0tx";
  813. dmas = <0x18 0x03 0x18 0x03>;
  814. interrupts = <0x00 0x0d 0x04>;
  815. phandle = <0x68>;
  816. reg = <0x1c22000 0x400>;
  817. resets = <0x03 0x2b>;
  818. status = "disabled";
  819. };
  820.  
  821. i2s@1c22400 {
  822. #sound-dai-cells = <0x00>;
  823. clock-names = "apb\0mod";
  824. clocks = <0x03 0x39 0x03 0x55>;
  825. compatible = "allwinner,sun8i-h3-i2s";
  826. dma-names = "rx\0tx";
  827. dmas = <0x18 0x04 0x18 0x04>;
  828. interrupts = <0x00 0x0e 0x04>;
  829. phandle = <0x69>;
  830. reg = <0x1c22400 0x400>;
  831. resets = <0x03 0x2c>;
  832. status = "disabled";
  833. };
  834.  
  835. i2s@1c22800 {
  836. #sound-dai-cells = <0x00>;
  837. clock-names = "apb\0mod";
  838. clocks = <0x03 0x3a 0x03 0x56>;
  839. compatible = "allwinner,sun8i-h3-i2s";
  840. dma-names = "tx";
  841. dmas = <0x18 0x1b>;
  842. interrupts = <0x00 0x0f 0x04>;
  843. phandle = <0x06>;
  844. reg = <0x1c22800 0x400>;
  845. resets = <0x03 0x2d>;
  846. status = "disabled";
  847. };
  848.  
  849. interrupt-controller@1c81000 {
  850. #interrupt-cells = <0x03>;
  851. compatible = "arm,gic-400";
  852. interrupt-controller;
  853. interrupts = <0x01 0x09 0xf04>;
  854. phandle = <0x01>;
  855. reg = <0x1c81000 0x1000 0x1c82000 0x2000 0x1c84000 0x2000 0x1c86000 0x2000>;
  856. };
  857.  
  858. interrupt-controller@1f00c00 {
  859. #interrupt-cells = <0x03>;
  860. compatible = "allwinner,sun8i-h3-r-intc\0allwinner,sun6i-a31-r-intc";
  861. interrupt-controller;
  862. interrupts = <0x00 0x20 0x04>;
  863. phandle = <0x15>;
  864. reg = <0x1f00c00 0x400>;
  865. };
  866.  
  867. ir@1f02000 {
  868. clock-names = "apb\0ir";
  869. clocks = <0x2c 0x04 0x2c 0x0b>;
  870. compatible = "allwinner,sun6i-a31-ir";
  871. interrupts = <0x00 0x25 0x04>;
  872. phandle = <0x76>;
  873. reg = <0x1f02000 0x400>;
  874. resets = <0x2c 0x00>;
  875. status = "disabled";
  876. };
  877.  
  878. lcd-controller@1c0c000 {
  879. clock-names = "ahb\0tcon-ch1";
  880. clocks = <0x03 0x2a 0x03 0x66>;
  881. compatible = "allwinner,sun8i-h3-tcon-tv\0allwinner,sun8i-a83t-tcon-tv";
  882. interrupts = <0x00 0x56 0x04>;
  883. phandle = <0x46>;
  884. reg = <0x1c0c000 0x1000>;
  885. reset-names = "lcd";
  886. resets = <0x03 0x1b>;
  887.  
  888. ports {
  889. #address-cells = <0x01>;
  890. #size-cells = <0x00>;
  891.  
  892. port@0 {
  893. phandle = <0x47>;
  894. reg = <0x00>;
  895.  
  896. endpoint {
  897. phandle = <0x09>;
  898. remote-endpoint = <0x0a>;
  899. };
  900. };
  901.  
  902. port@1 {
  903. #address-cells = <0x01>;
  904. #size-cells = <0x00>;
  905. phandle = <0x48>;
  906. reg = <0x01>;
  907.  
  908. endpoint@1 {
  909. phandle = <0x2a>;
  910. reg = <0x01>;
  911. remote-endpoint = <0x0b>;
  912. };
  913. };
  914. };
  915. };
  916.  
  917. mailbox@1c17000 {
  918. #mbox-cells = <0x01>;
  919. clocks = <0x03 0x32>;
  920. compatible = "allwinner,sun8i-h3-msgbox\0allwinner,sun6i-a31-msgbox";
  921. interrupts = <0x00 0x31 0x04>;
  922. phandle = <0x07>;
  923. reg = <0x1c17000 0x1000>;
  924. resets = <0x03 0x24>;
  925. };
  926.  
  927. mixer@1100000 {
  928. clock-names = "bus\0mod";
  929. clocks = <0x02 0x00 0x02 0x06>;
  930. compatible = "allwinner,sun8i-h3-de2-mixer-0";
  931. phandle = <0x04>;
  932. reg = <0x1100000 0x100000>;
  933. resets = <0x02 0x00>;
  934.  
  935. ports {
  936. #address-cells = <0x01>;
  937. #size-cells = <0x00>;
  938.  
  939. port@1 {
  940. phandle = <0x45>;
  941. reg = <0x01>;
  942.  
  943. endpoint {
  944. phandle = <0x0a>;
  945. remote-endpoint = <0x09>;
  946. };
  947. };
  948. };
  949. };
  950.  
  951. mmc@1c0f000 {
  952. #address-cells = <0x01>;
  953. #size-cells = <0x00>;
  954. bus-width = <0x04>;
  955. cd-gpios = <0x0e 0x05 0x06 0x01>;
  956. clock-names = "ahb\0mmc\0output\0sample";
  957. clocks = <0x03 0x16 0x03 0x47 0x03 0x49 0x03 0x48>;
  958. compatible = "allwinner,sun7i-a20-mmc";
  959. interrupts = <0x00 0x3c 0x04>;
  960. phandle = <0x49>;
  961. pinctrl-0 = <0x0c>;
  962. pinctrl-names = "default";
  963. reg = <0x1c0f000 0x1000>;
  964. reset-names = "ahb";
  965. resets = <0x03 0x07>;
  966. status = "okay";
  967. vmmc-supply = <0x0d>;
  968. };
  969.  
  970. mmc@1c10000 {
  971. #address-cells = <0x01>;
  972. #size-cells = <0x00>;
  973. bus-width = <0x04>;
  974. clock-names = "ahb\0mmc\0output\0sample";
  975. clocks = <0x03 0x17 0x03 0x4a 0x03 0x4c 0x03 0x4b>;
  976. compatible = "allwinner,sun7i-a20-mmc";
  977. interrupts = <0x00 0x3d 0x04>;
  978. mmc-pwrseq = <0x10>;
  979. non-removable;
  980. phandle = <0x4a>;
  981. pinctrl-0 = <0x0f>;
  982. pinctrl-names = "default";
  983. reg = <0x1c10000 0x1000>;
  984. reset-names = "ahb";
  985. resets = <0x03 0x08>;
  986. status = "okay";
  987. vmmc-supply = <0x0d>;
  988. vqmmc-supply = <0x0d>;
  989.  
  990. bcrmf@1 {
  991. compatible = "brcm,bcm4329-fmac";
  992. interrupt-names = "host-wake";
  993. interrupt-parent = <0x0e>;
  994. interrupts = <0x06 0x0a 0x08>;
  995. phandle = <0x4b>;
  996. reg = <0x01>;
  997. };
  998. };
  999.  
  1000. mmc@1c11000 {
  1001. #address-cells = <0x01>;
  1002. #size-cells = <0x00>;
  1003. bus-width = <0x08>;
  1004. cap-mmc-hw-reset;
  1005. clock-names = "ahb\0mmc\0output\0sample";
  1006. clocks = <0x03 0x18 0x03 0x4d 0x03 0x4f 0x03 0x4e>;
  1007. compatible = "allwinner,sun7i-a20-mmc";
  1008. interrupts = <0x00 0x3e 0x04>;
  1009. non-removable;
  1010. phandle = <0x4c>;
  1011. pinctrl-0 = <0x11>;
  1012. pinctrl-names = "default";
  1013. reg = <0x1c11000 0x1000>;
  1014. reset-names = "ahb";
  1015. resets = <0x03 0x09>;
  1016. status = "okay";
  1017. vmmc-supply = <0x0d>;
  1018. };
  1019.  
  1020. phy@1c19400 {
  1021. #phy-cells = <0x01>;
  1022. clock-names = "usb0_phy\0usb1_phy\0usb2_phy\0usb3_phy";
  1023. clocks = <0x03 0x58 0x03 0x59 0x03 0x5a 0x03 0x5b>;
  1024. compatible = "allwinner,sun8i-h3-usb-phy";
  1025. phandle = <0x12>;
  1026. reg = <0x1c19400 0x2c 0x1c1a800 0x04 0x1c1b800 0x04 0x1c1c800 0x04 0x1c1d800 0x04>;
  1027. reg-names = "phy_ctrl\0pmu0\0pmu1\0pmu2\0pmu3";
  1028. reset-names = "usb0_reset\0usb1_reset\0usb2_reset\0usb3_reset";
  1029. resets = <0x03 0x00 0x03 0x01 0x03 0x02 0x03 0x03>;
  1030. status = "okay";
  1031. };
  1032.  
  1033. pinctrl@1c20800 {
  1034. #gpio-cells = <0x03>;
  1035. #interrupt-cells = <0x03>;
  1036. clock-names = "apb\0hosc\0losc";
  1037. clocks = <0x03 0x36 0x13 0x14 0x00>;
  1038. compatible = "allwinner,sun8i-h3-pinctrl";
  1039. gpio-controller;
  1040. interrupt-controller;
  1041. interrupt-parent = <0x15>;
  1042. interrupts = <0x00 0x0b 0x04 0x00 0x11 0x04>;
  1043. phandle = <0x0e>;
  1044. pinctrl-0 = <0x86>;
  1045. reg = <0x1c20800 0x400>;
  1046.  
  1047. bt_pwr_pin@0 {
  1048. function = "gpio_out";
  1049. phandle = <0x41>;
  1050. pins = "PG13";
  1051. };
  1052.  
  1053. csi-pins {
  1054. function = "csi";
  1055. phandle = <0x27>;
  1056. pins = "PE0\0PE2\0PE3\0PE4\0PE5\0PE6\0PE7\0PE8\0PE9\0PE10\0PE11";
  1057. };
  1058.  
  1059. emac-rgmii-pins {
  1060. drive-strength = <0x28>;
  1061. function = "emac";
  1062. phandle = <0x57>;
  1063. pins = "PD0\0PD1\0PD2\0PD3\0PD4\0PD5\0PD7\0PD8\0PD9\0PD10\0PD12\0PD13\0PD15\0PD16\0PD17";
  1064. };
  1065.  
  1066. i2c0-pins {
  1067. function = "i2c0";
  1068. phandle = <0x1f>;
  1069. pins = "PA11\0PA12";
  1070. };
  1071.  
  1072. i2c1-pins {
  1073. function = "i2c1";
  1074. phandle = <0x20>;
  1075. pins = "PA18\0PA19";
  1076. };
  1077.  
  1078. i2c2-pins {
  1079. bias-pull-up;
  1080. function = "i2c2";
  1081. phandle = <0x21>;
  1082. pins = "PE12\0PE13";
  1083. };
  1084.  
  1085. i2s0-pins {
  1086. function = "i2s0";
  1087. phandle = <0x58>;
  1088. pins = "PA18\0PA19\0PA20\0PA21";
  1089. };
  1090.  
  1091. i2s1-pins {
  1092. function = "i2s1";
  1093. phandle = <0x59>;
  1094. pins = "PG10\0PG11\0PG12\0PG13";
  1095. };
  1096.  
  1097. mmc0-pins {
  1098. bias-pull-up;
  1099. drive-strength = <0x1e>;
  1100. function = "mmc0";
  1101. phandle = <0x0c>;
  1102. pins = "PF0\0PF1\0PF2\0PF3\0PF4\0PF5";
  1103. };
  1104.  
  1105. mmc1-pins {
  1106. bias-pull-up;
  1107. drive-strength = <0x1e>;
  1108. function = "mmc1";
  1109. phandle = <0x0f>;
  1110. pins = "PG0\0PG1\0PG2\0PG3\0PG4\0PG5";
  1111. };
  1112.  
  1113. mmc2-8bit-pins {
  1114. bias-pull-up;
  1115. drive-strength = <0x28>;
  1116. function = "mmc2";
  1117. phandle = <0x11>;
  1118. pins = "PC5\0PC6\0PC8\0PC9\0PC10\0PC11\0PC12\0PC13\0PC14\0PC15\0PC16";
  1119. };
  1120.  
  1121. pull_pins {
  1122. bias-disable;
  1123. function = "gpio_out";
  1124. output-low;
  1125. phandle = <0x86>;
  1126. pins = "PA6";
  1127. };
  1128.  
  1129. spdif-tx-pin {
  1130. function = "spdif";
  1131. phandle = <0x5a>;
  1132. pins = "PA17";
  1133. };
  1134.  
  1135. spi0-pins {
  1136. function = "spi0";
  1137. phandle = <0x19>;
  1138. pins = "PC0\0PC2";
  1139. };
  1140.  
  1141. spi1-pins {
  1142. function = "spi1";
  1143. phandle = <0x1a>;
  1144. pins = "PA15\0PA16\0PA14\0PA13";
  1145. };
  1146.  
  1147. uart0-pa-pins {
  1148. function = "uart0";
  1149. phandle = <0x1c>;
  1150. pins = "PA4\0PA5";
  1151. };
  1152.  
  1153. uart1-pins {
  1154. function = "uart1";
  1155. phandle = <0x5b>;
  1156. pins = "PG6\0PG7";
  1157. };
  1158.  
  1159. uart1-rts-cts-pins {
  1160. function = "uart1";
  1161. phandle = <0x5c>;
  1162. pins = "PG8\0PG9";
  1163. };
  1164.  
  1165. uart2-pins {
  1166. function = "uart2";
  1167. phandle = <0x5d>;
  1168. pins = "PA0\0PA1";
  1169. };
  1170.  
  1171. uart2-rts-cts-pins {
  1172. function = "uart2";
  1173. phandle = <0x5e>;
  1174. pins = "PA2\0PA3";
  1175. };
  1176.  
  1177. uart3-pins {
  1178. function = "uart3";
  1179. phandle = <0x1d>;
  1180. pins = "PA13\0PA14";
  1181. };
  1182.  
  1183. uart3-rts-cts-pins {
  1184. function = "uart3";
  1185. phandle = <0x1e>;
  1186. pins = "PA15\0PA16";
  1187. };
  1188. };
  1189.  
  1190. pinctrl@1f02c00 {
  1191. #gpio-cells = <0x03>;
  1192. #interrupt-cells = <0x03>;
  1193. clock-names = "apb\0hosc\0losc";
  1194. clocks = <0x2c 0x03 0x13 0x14 0x00>;
  1195. compatible = "allwinner,sun8i-h3-r-pinctrl";
  1196. gpio-controller;
  1197. interrupt-controller;
  1198. interrupt-parent = <0x15>;
  1199. interrupts = <0x00 0x2d 0x04>;
  1200. phandle = <0x3f>;
  1201. reg = <0x1f02c00 0x400>;
  1202.  
  1203. r-i2c-pins {
  1204. function = "s_i2c";
  1205. phandle = <0x2d>;
  1206. pins = "PL0\0PL1";
  1207. };
  1208.  
  1209. r-ir-rx-pin {
  1210. function = "s_cir_rx";
  1211. phandle = <0x78>;
  1212. pins = "PL11";
  1213. };
  1214.  
  1215. r-pwm-pin {
  1216. function = "s_pwm";
  1217. phandle = <0x2e>;
  1218. pins = "PL10";
  1219. };
  1220.  
  1221. wifi_en_pin {
  1222. function = "gpio_out";
  1223. phandle = <0x40>;
  1224. pins = "PL7";
  1225. };
  1226. };
  1227.  
  1228. pwm@1c21400 {
  1229. #pwm-cells = <0x03>;
  1230. clocks = <0x13>;
  1231. compatible = "allwinner,sun8i-h3-pwm";
  1232. phandle = <0x67>;
  1233. reg = <0x1c21400 0x08>;
  1234. status = "disabled";
  1235. };
  1236.  
  1237. pwm@1f03800 {
  1238. #pwm-cells = <0x03>;
  1239. clocks = <0x13>;
  1240. compatible = "allwinner,sun8i-h3-pwm";
  1241. phandle = <0x79>;
  1242. pinctrl-0 = <0x2e>;
  1243. pinctrl-names = "default";
  1244. reg = <0x1f03800 0x08>;
  1245. status = "disabled";
  1246. };
  1247.  
  1248. rtc@1f00000 {
  1249. #clock-cells = <0x01>;
  1250. clock-output-names = "osc32k\0osc32k-out\0iosc";
  1251. clocks = <0x2b>;
  1252. compatible = "allwinner,sun8i-h3-rtc";
  1253. interrupt-parent = <0x15>;
  1254. interrupts = <0x00 0x28 0x04 0x00 0x29 0x04>;
  1255. phandle = <0x14>;
  1256. reg = <0x1f00000 0x400>;
  1257. };
  1258.  
  1259. serial@1c28000 {
  1260. clocks = <0x03 0x3e>;
  1261. compatible = "snps,dw-apb-uart";
  1262. dma-names = "rx\0tx";
  1263. dmas = <0x18 0x06 0x18 0x06>;
  1264. interrupts = <0x00 0x00 0x04>;
  1265. phandle = <0x6b>;
  1266. pinctrl-0 = <0x1c>;
  1267. pinctrl-names = "default";
  1268. reg = <0x1c28000 0x400>;
  1269. reg-io-width = <0x04>;
  1270. reg-shift = <0x02>;
  1271. resets = <0x03 0x31>;
  1272. status = "okay";
  1273. };
  1274.  
  1275. serial@1c28400 {
  1276. clocks = <0x03 0x3f>;
  1277. compatible = "snps,dw-apb-uart";
  1278. dma-names = "rx\0tx";
  1279. dmas = <0x18 0x07 0x18 0x07>;
  1280. interrupts = <0x00 0x01 0x04>;
  1281. phandle = <0x6c>;
  1282. reg = <0x1c28400 0x400>;
  1283. reg-io-width = <0x04>;
  1284. reg-shift = <0x02>;
  1285. resets = <0x03 0x32>;
  1286. status = "disabled";
  1287. };
  1288.  
  1289. serial@1c28800 {
  1290. clocks = <0x03 0x40>;
  1291. compatible = "snps,dw-apb-uart";
  1292. dma-names = "rx\0tx";
  1293. dmas = <0x18 0x08 0x18 0x08>;
  1294. interrupts = <0x00 0x02 0x04>;
  1295. phandle = <0x6d>;
  1296. reg = <0x1c28800 0x400>;
  1297. reg-io-width = <0x04>;
  1298. reg-shift = <0x02>;
  1299. resets = <0x03 0x33>;
  1300. status = "disabled";
  1301. };
  1302.  
  1303. serial@1c28c00 {
  1304. clocks = <0x03 0x41>;
  1305. compatible = "snps,dw-apb-uart";
  1306. dma-names = "rx\0tx";
  1307. dmas = <0x18 0x09 0x18 0x09>;
  1308. interrupts = <0x00 0x03 0x04>;
  1309. phandle = <0x6e>;
  1310. pinctrl-0 = <0x1d 0x1e>;
  1311. pinctrl-names = "default";
  1312. reg = <0x1c28c00 0x400>;
  1313. reg-io-width = <0x04>;
  1314. reg-shift = <0x02>;
  1315. resets = <0x03 0x34>;
  1316. status = "okay";
  1317. };
  1318.  
  1319. spdif@1c21000 {
  1320. #sound-dai-cells = <0x00>;
  1321. clock-names = "apb\0spdif";
  1322. clocks = <0x03 0x35 0x03 0x57>;
  1323. compatible = "allwinner,sun8i-h3-spdif";
  1324. dma-names = "tx";
  1325. dmas = <0x18 0x02>;
  1326. interrupts = <0x00 0x0c 0x04>;
  1327. phandle = <0x66>;
  1328. reg = <0x1c21000 0x400>;
  1329. resets = <0x03 0x29>;
  1330. status = "disabled";
  1331. };
  1332.  
  1333. spi@1c68000 {
  1334. #address-cells = <0x01>;
  1335. #cs-gpios = <0x0e 0x02 0x03 0x00>;
  1336. #size-cells = <0x00>;
  1337. clock-names = "ahb\0mod";
  1338. clocks = <0x03 0x1e 0x03 0x52>;
  1339. compatible = "allwinner,sun8i-h3-spi";
  1340. dma-names = "rx\0tx";
  1341. dmas = <0x18 0x17 0x18 0x17>;
  1342. interrupts = <0x00 0x41 0x04>;
  1343. num-cs = <0x01>;
  1344. phandle = <0x63>;
  1345. pinctrl-0 = <0x19>;
  1346. pinctrl-names = "default";
  1347. reg = <0x1c68000 0x1000>;
  1348. resets = <0x03 0x0f>;
  1349. status = "okay";
  1350.  
  1351. st7789@0 {
  1352. buswidth = <0x08>;
  1353. compatible = "sitronix,st7789v";
  1354. dc-gpios = <0x0e 0x06 0x09 0x00>;
  1355. debug = <0x01>;
  1356. height = <0xf0>;
  1357. phandle = <0x87>;
  1358. reg = <0x00>;
  1359. reset-gpios = <0x0e 0x06 0x08 0x01>;
  1360. rotate = <0x00>;
  1361. spi-cpha;
  1362. spi-cpol;
  1363. spi-max-frequency = <0x989680>;
  1364. width = <0xf0>;
  1365. };
  1366. };
  1367.  
  1368. spi@1c69000 {
  1369. #address-cells = <0x01>;
  1370. #size-cells = <0x00>;
  1371. clock-names = "ahb\0mod";
  1372. clocks = <0x03 0x1f 0x03 0x53>;
  1373. compatible = "allwinner,sun8i-h3-spi";
  1374. dma-names = "rx\0tx";
  1375. dmas = <0x18 0x18 0x18 0x18>;
  1376. interrupts = <0x00 0x42 0x04>;
  1377. phandle = <0x64>;
  1378. pinctrl-0 = <0x1a>;
  1379. pinctrl-names = "default";
  1380. reg = <0x1c69000 0x1000>;
  1381. resets = <0x03 0x10>;
  1382. status = "disabled";
  1383. };
  1384.  
  1385. system-control@1c00000 {
  1386. #address-cells = <0x01>;
  1387. #size-cells = <0x01>;
  1388. compatible = "allwinner,sun8i-h3-system-control";
  1389. phandle = <0x16>;
  1390. ranges;
  1391. reg = <0x1c00000 0x1000>;
  1392.  
  1393. sram@1d00000 {
  1394. #address-cells = <0x01>;
  1395. #size-cells = <0x01>;
  1396. compatible = "mmio-sram";
  1397. phandle = <0x7c>;
  1398. ranges = <0x00 0x1d00000 0x80000>;
  1399. reg = <0x1d00000 0x80000>;
  1400.  
  1401. sram-section@0 {
  1402. compatible = "allwinner,sun8i-h3-sram-c1\0allwinner,sun4i-a10-sram-c1";
  1403. phandle = <0x30>;
  1404. reg = <0x00 0x80000>;
  1405. };
  1406. };
  1407.  
  1408. sram@40000 {
  1409. #address-cells = <0x01>;
  1410. #size-cells = <0x01>;
  1411. compatible = "mmio-sram";
  1412. phandle = <0x7b>;
  1413. ranges = <0x00 0x40000 0xc000>;
  1414. reg = <0x40000 0xc000>;
  1415.  
  1416. scp-shmem@bc00 {
  1417. compatible = "arm,scp-shmem";
  1418. phandle = <0x08>;
  1419. reg = <0xbc00 0x200>;
  1420. };
  1421. };
  1422. };
  1423.  
  1424. thermal-sensor@1c25000 {
  1425. #thermal-sensor-cells = <0x00>;
  1426. clock-names = "bus\0mod";
  1427. clocks = <0x03 0x37 0x03 0x45>;
  1428. compatible = "allwinner,sun8i-h3-ths";
  1429. interrupts = <0x00 0x1f 0x04>;
  1430. nvmem-cell-names = "calibration";
  1431. nvmem-cells = <0x32>;
  1432. phandle = <0x39>;
  1433. reg = <0x1c25000 0x400>;
  1434. resets = <0x03 0x2a>;
  1435. };
  1436.  
  1437. timer@1c20c00 {
  1438. clocks = <0x13>;
  1439. compatible = "allwinner,sun8i-a23-timer";
  1440. interrupts = <0x00 0x12 0x04 0x00 0x13 0x04>;
  1441. reg = <0x1c20c00 0xa0>;
  1442. };
  1443.  
  1444. usb@1c19000 {
  1445. clocks = <0x03 0x20>;
  1446. compatible = "allwinner,sun8i-h3-musb";
  1447. dr_mode = "peripheral";
  1448. extcon = <0x12 0x00>;
  1449. interrupt-names = "mc";
  1450. interrupts = <0x00 0x47 0x04>;
  1451. phandle = <0x4e>;
  1452. phy-names = "usb";
  1453. phys = <0x12 0x00>;
  1454. reg = <0x1c19000 0x400>;
  1455. resets = <0x03 0x11>;
  1456. status = "okay";
  1457. };
  1458.  
  1459. usb@1c1a000 {
  1460. clocks = <0x03 0x21 0x03 0x25>;
  1461. compatible = "allwinner,sun8i-h3-ehci\0generic-ehci";
  1462. interrupts = <0x00 0x48 0x04>;
  1463. phandle = <0x4f>;
  1464. reg = <0x1c1a000 0x100>;
  1465. resets = <0x03 0x12 0x03 0x16>;
  1466. status = "okay";
  1467. };
  1468.  
  1469. usb@1c1a400 {
  1470. clocks = <0x03 0x21 0x03 0x25 0x03 0x5c>;
  1471. compatible = "allwinner,sun8i-h3-ohci\0generic-ohci";
  1472. interrupts = <0x00 0x49 0x04>;
  1473. phandle = <0x50>;
  1474. reg = <0x1c1a400 0x100>;
  1475. resets = <0x03 0x12 0x03 0x16>;
  1476. status = "okay";
  1477. };
  1478.  
  1479. usb@1c1b000 {
  1480. clocks = <0x03 0x22 0x03 0x26>;
  1481. compatible = "allwinner,sun8i-h3-ehci\0generic-ehci";
  1482. interrupts = <0x00 0x4a 0x04>;
  1483. phandle = <0x51>;
  1484. phy-names = "usb";
  1485. phys = <0x12 0x01>;
  1486. reg = <0x1c1b000 0x100>;
  1487. resets = <0x03 0x13 0x03 0x17>;
  1488. status = "disabled";
  1489. };
  1490.  
  1491. usb@1c1b400 {
  1492. clocks = <0x03 0x22 0x03 0x26 0x03 0x5d>;
  1493. compatible = "allwinner,sun8i-h3-ohci\0generic-ohci";
  1494. interrupts = <0x00 0x4b 0x04>;
  1495. phandle = <0x52>;
  1496. phy-names = "usb";
  1497. phys = <0x12 0x01>;
  1498. reg = <0x1c1b400 0x100>;
  1499. resets = <0x03 0x13 0x03 0x17>;
  1500. status = "disabled";
  1501. };
  1502.  
  1503. usb@1c1c000 {
  1504. clocks = <0x03 0x23 0x03 0x27>;
  1505. compatible = "allwinner,sun8i-h3-ehci\0generic-ehci";
  1506. interrupts = <0x00 0x4c 0x04>;
  1507. phandle = <0x53>;
  1508. phy-names = "usb";
  1509. phys = <0x12 0x02>;
  1510. reg = <0x1c1c000 0x100>;
  1511. resets = <0x03 0x14 0x03 0x18>;
  1512. status = "okay";
  1513. };
  1514.  
  1515. usb@1c1c400 {
  1516. clocks = <0x03 0x23 0x03 0x27 0x03 0x5e>;
  1517. compatible = "allwinner,sun8i-h3-ohci\0generic-ohci";
  1518. interrupts = <0x00 0x4d 0x04>;
  1519. phandle = <0x54>;
  1520. phy-names = "usb";
  1521. phys = <0x12 0x02>;
  1522. reg = <0x1c1c400 0x100>;
  1523. resets = <0x03 0x14 0x03 0x18>;
  1524. status = "okay";
  1525. };
  1526.  
  1527. usb@1c1d000 {
  1528. clocks = <0x03 0x24 0x03 0x28>;
  1529. compatible = "allwinner,sun8i-h3-ehci\0generic-ehci";
  1530. interrupts = <0x00 0x4e 0x04>;
  1531. phandle = <0x55>;
  1532. phy-names = "usb";
  1533. phys = <0x12 0x03>;
  1534. reg = <0x1c1d000 0x100>;
  1535. resets = <0x03 0x15 0x03 0x19>;
  1536. status = "okay";
  1537. };
  1538.  
  1539. usb@1c1d400 {
  1540. clocks = <0x03 0x24 0x03 0x28 0x03 0x5f>;
  1541. compatible = "allwinner,sun8i-h3-ohci\0generic-ohci";
  1542. interrupts = <0x00 0x4f 0x04>;
  1543. phandle = <0x56>;
  1544. phy-names = "usb";
  1545. phys = <0x12 0x03>;
  1546. reg = <0x1c1d400 0x100>;
  1547. resets = <0x03 0x15 0x03 0x19>;
  1548. status = "okay";
  1549. };
  1550.  
  1551. video-codec@1c0e000 {
  1552. allwinner,sram = <0x30 0x01>;
  1553. clock-names = "ahb\0mod\0ram";
  1554. clocks = <0x03 0x29 0x03 0x6c 0x03 0x61>;
  1555. compatible = "allwinner,sun8i-h3-video-engine";
  1556. interrupts = <0x00 0x3a 0x04>;
  1557. reg = <0x1c0e000 0x1000>;
  1558. resets = <0x03 0x1a>;
  1559. };
  1560.  
  1561. watchdog@1c20ca0 {
  1562. clocks = <0x13>;
  1563. compatible = "allwinner,sun6i-a31-wdt";
  1564. interrupts = <0x00 0x19 0x04>;
  1565. phandle = <0x65>;
  1566. reg = <0x1c20ca0 0x20>;
  1567. };
  1568. };
  1569.  
  1570. sound_hdmi {
  1571. compatible = "allwinner,sun9i-a80-hdmi-audio\0allwinner,sun8i-h3-hdmi-audio";
  1572. phandle = <0x43>;
  1573. status = "disabled";
  1574.  
  1575. codec {
  1576. sound-dai = <0x05>;
  1577. };
  1578.  
  1579. cpu {
  1580. sound-dai = <0x06>;
  1581. };
  1582. };
  1583.  
  1584. thermal-zones {
  1585.  
  1586. cpu_thermal {
  1587. polling-delay = <0x3e8>;
  1588. polling-delay-passive = <0xfa>;
  1589. thermal-sensors = <0x39>;
  1590.  
  1591. cooling-maps {
  1592.  
  1593. cpu_hot_limit_cpu {
  1594. cooling-device = <0x35 0x03 0x04>;
  1595. trip = <0x3c>;
  1596. };
  1597.  
  1598. cpu_hot_pre_limit_cpu {
  1599. cooling-device = <0x35 0x02 0x03>;
  1600. trip = <0x3b>;
  1601. };
  1602.  
  1603. cpu_very_hot_limit_cpu {
  1604. cooling-device = <0x35 0x07 0xffffffff>;
  1605. trip = <0x3e>;
  1606. };
  1607.  
  1608. cpu_very_hot_pre_limit_cpu {
  1609. cooling-device = <0x35 0x05 0x06>;
  1610. trip = <0x3d>;
  1611. };
  1612.  
  1613. cpu_warm_limit_cpu {
  1614. cooling-device = <0x35 0xffffffff 0x02>;
  1615. trip = <0x3a>;
  1616. };
  1617. };
  1618.  
  1619. trips {
  1620.  
  1621. cpu_crit {
  1622. hysteresis = <0x7d0>;
  1623. phandle = <0x7f>;
  1624. temperature = <0x19a28>;
  1625. type = "critical";
  1626. };
  1627.  
  1628. cpu_hot {
  1629. hysteresis = <0x7d0>;
  1630. phandle = <0x3c>;
  1631. temperature = <0x14c08>;
  1632. type = "passive";
  1633. };
  1634.  
  1635. cpu_hot_pre {
  1636. hysteresis = <0x7d0>;
  1637. phandle = <0x3b>;
  1638. temperature = <0x13880>;
  1639. type = "passive";
  1640. };
  1641.  
  1642. cpu_very_hot {
  1643. hysteresis = <0x7d0>;
  1644. phandle = <0x3e>;
  1645. temperature = <0x17318>;
  1646. type = "passive";
  1647. };
  1648.  
  1649. cpu_very_hot_pre {
  1650. hysteresis = <0x7d0>;
  1651. phandle = <0x3d>;
  1652. temperature = <0x15f90>;
  1653. type = "passive";
  1654. };
  1655.  
  1656. cpu_warm {
  1657. hysteresis = <0x7d0>;
  1658. phandle = <0x3a>;
  1659. temperature = <0x124f8>;
  1660. type = "passive";
  1661. };
  1662. };
  1663. };
  1664. };
  1665.  
  1666. timer {
  1667. compatible = "arm,armv7-timer";
  1668. interrupts = <0x01 0x0d 0xf08 0x01 0x0e 0xf08 0x01 0x0b 0xf08 0x01 0x0a 0xf08>;
  1669. };
  1670.  
  1671. usb0-vbus {
  1672. compatible = "regulator-fixed";
  1673. enable-active-high;
  1674. gpio = <0x0e 0x01 0x09 0x00>;
  1675. phandle = <0x81>;
  1676. regulator-max-microvolt = <0x4c4b40>;
  1677. regulator-min-microvolt = <0x4c4b40>;
  1678. regulator-name = "usb0-vbus";
  1679. status = "disabled";
  1680. };
  1681.  
  1682. usb1-vbus {
  1683. compatible = "regulator-fixed";
  1684. enable-active-high;
  1685. gpio = <0x0e 0x07 0x06 0x00>;
  1686. phandle = <0x82>;
  1687. regulator-boot-on;
  1688. regulator-max-microvolt = <0x4c4b40>;
  1689. regulator-min-microvolt = <0x4c4b40>;
  1690. regulator-name = "usb1-vbus";
  1691. status = "disabled";
  1692. };
  1693.  
  1694. usb2-vbus {
  1695. compatible = "regulator-fixed";
  1696. enable-active-high;
  1697. gpio = <0x0e 0x07 0x03 0x00>;
  1698. phandle = <0x83>;
  1699. regulator-boot-on;
  1700. regulator-max-microvolt = <0x4c4b40>;
  1701. regulator-min-microvolt = <0x4c4b40>;
  1702. regulator-name = "usb2-vbus";
  1703. status = "disabled";
  1704. };
  1705.  
  1706. vcc3v0 {
  1707. compatible = "regulator-fixed";
  1708. phandle = <0x84>;
  1709. regulator-max-microvolt = <0x2dc6c0>;
  1710. regulator-min-microvolt = <0x2dc6c0>;
  1711. regulator-name = "vcc3v0";
  1712. };
  1713.  
  1714. vcc3v3 {
  1715. compatible = "regulator-fixed";
  1716. phandle = <0x0d>;
  1717. regulator-max-microvolt = <0x325aa0>;
  1718. regulator-min-microvolt = <0x325aa0>;
  1719. regulator-name = "vcc3v3";
  1720. };
  1721.  
  1722. vcc5v0 {
  1723. compatible = "regulator-fixed";
  1724. phandle = <0x85>;
  1725. regulator-max-microvolt = <0x4c4b40>;
  1726. regulator-min-microvolt = <0x4c4b40>;
  1727. regulator-name = "vcc5v0";
  1728. };
  1729.  
  1730. wifi_pwrseq {
  1731. compatible = "mmc-pwrseq-simple";
  1732. phandle = <0x10>;
  1733. pinctrl-0 = <0x40>;
  1734. pinctrl-names = "default";
  1735. post-power-on-delay-ms = <0xc8>;
  1736. reset-gpios = <0x3f 0x00 0x07 0x01>;
  1737. };
  1738. };
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