API tools faq
paste
Advertisement
xiahanlu

arm7芯片源码 草稿

xiahanlu
Jul 24th, 2019
285
0
Never
Add comment
Not a member of Pastebin yet? Sign Up, it unlocks many cool features!
C 195.41 KB | None | 0 0
raw download clone embed print report
  1.  
  2. #ifndef ARM7TDMI_INL
  3. #define ARM7TDMI_INL 1
  4.  
  5. #include "gba.h"
  6. #include "mbus.inl"
  7.  
  8. /* =================== ARM7 HELPER =================== */
  9. struct arm_alu_rot_imm32 {
  10.   uint32_t immed_8:8;
  11.   uint32_t rorate_imm:4;
  12.   uint32_t rd:4;
  13.   uint32_t rn:4;
  14.   uint32_t s:1;
  15.   uint32_t opcode:4;
  16.   uint32_t _0_0_1:3;
  17.   uint32_t cond:4;
  18. };
  19. struct arm_alu_shift_imm5 {
  20.   uint32_t rm:4;
  21.   uint32_t _0:1;
  22.   uint32_t shift:2;
  23.   uint32_t shift_imm:5;
  24.   uint32_t rd:4;
  25.   uint32_t rn:4;
  26.   uint32_t s:1;
  27.   uint32_t opcode:4;
  28.   uint32_t _0_0_0:3;
  29.   uint32_t cond:4;
  30. };
  31. struct arm_alu_shift_rs {
  32.   uint32_t rm:4;
  33.   uint32_t _1:1;
  34.   uint32_t shift:2;
  35.   uint32_t _0:1;
  36.   uint32_t rs:4;
  37.   uint32_t rd:4;
  38.   uint32_t rn:4;
  39.   uint32_t s:1;
  40.   uint32_t opcode:4;
  41.   uint32_t _0_0_0:3;
  42.   uint32_t cond:4;
  43. };
  44. struct arm_memory_access_ubw_imm12 {
  45.   uint32_t offset12:12;
  46.   uint32_t rd:4;
  47.   uint32_t rn:4;
  48.   uint32_t l:1;
  49.   uint32_t w:1;
  50.   uint32_t b:1;
  51.   uint32_t u:1;
  52.   uint32_t p:1;
  53.   uint32_t _0_1_0:3;
  54.   uint32_t cond:4;
  55. };
  56. struct arm_memory_access_ubw_reg {
  57.   uint32_t rm:4;
  58.   uint32_t _0_0_0_0_0_0_0_0:8;
  59.   uint32_t rd:4;
  60.   uint32_t rn:4;
  61.   uint32_t l:1;
  62.   uint32_t w:1;
  63.   uint32_t b:1;
  64.   uint32_t u:1;
  65.   uint32_t p:1;
  66.   uint32_t _0_1_1:3;
  67.   uint32_t cond:4;
  68. };
  69. struct arm_memory_access_ubw_scaled {
  70.   uint32_t rm:4;
  71.   uint32_t _0:1;
  72.   uint32_t shift:2;
  73.   uint32_t shift_imm:5;
  74.   uint32_t rd:4;
  75.   uint32_t rn:4;
  76.   uint32_t l:1;
  77.   uint32_t w:1;
  78.   uint32_t b:1;
  79.   uint32_t u:1;
  80.   uint32_t p:1;
  81.   uint32_t _0_1_1:3;
  82.   uint32_t cond:4;
  83. };
  84. struct arm_memory_access_sbh_imm8 {
  85.   uint32_t imm_l:4;
  86.   uint32_t _1:1;
  87.   uint32_t h:1;
  88.   uint32_t s:1;
  89.   uint32_t __1:1;
  90.   uint32_t imm_h:4;
  91.   uint32_t rd:4;
  92.   uint32_t rn:4;
  93.   uint32_t l:1;
  94.   uint32_t w:1;
  95.   uint32_t ___1:1;
  96.   uint32_t u:1;
  97.   uint32_t p:1;
  98.   uint32_t _0_0_0:3;
  99.   uint32_t cond:4;
  100. };
  101. struct arm_memory_access_sbh_reg {
  102.   uint32_t rm:4;
  103.   uint32_t _1:1;
  104.   uint32_t h:1;
  105.   uint32_t s:1;
  106.   uint32_t __1:1;
  107.   uint32_t sbz:4;
  108.   uint32_t rd:4;
  109.   uint32_t rn:4;
  110.   uint32_t l:1;
  111.   uint32_t w:1;
  112.   uint32_t _0:1;
  113.   uint32_t u:1;
  114.   uint32_t p:1;
  115.   uint32_t _0_0_0:3;
  116.   uint32_t cond:4;
  117. };
  118. struct arm_list_memory_access {
  119.   uint32_t r0:1;
  120.   uint32_t r1:1;
  121.   uint32_t r2:1;
  122.   uint32_t r3:1;
  123.   uint32_t r4:1;
  124.   uint32_t r5:1;
  125.   uint32_t r6:1;
  126.   uint32_t r7:1;
  127.   uint32_t r8:1;
  128.   uint32_t r9:1;
  129.   uint32_t r10:1;
  130.   uint32_t r11:1;
  131.   uint32_t r12:1;
  132.   uint32_t r13:1; /* sp */
  133.   uint32_t r14:1; /* lr */
  134.   uint32_t r15:1; /* pc */
  135.   uint32_t rn:4;
  136.   uint32_t l:1;
  137.   uint32_t w:1;
  138.   uint32_t s:1;
  139.   uint32_t u:1;
  140.   uint32_t p:1;
  141.   uint32_t _1_0_0:3;
  142.   uint32_t cond:4;
  143. };
  144. struct arm_atomic_memory_access {
  145.   uint32_t rm:4;
  146.   uint32_t _1_0_0_1:4;
  147.   uint32_t sbz:4;
  148.   uint32_t rd:4;
  149.   uint32_t rn:4;
  150.   uint32_t _0_0:2;
  151.   uint32_t b:1;
  152.   uint32_t _0_0_0_1_0:5;
  153.   uint32_t cond:4;
  154. };
  155. struct arm_swi {
  156.   uint32_t imm_24:24;
  157.   uint32_t _1_1_1_1:4;
  158.   uint32_t cond:4;
  159. };
  160. struct arm_mul {
  161.   uint32_t rm:4;
  162.   uint32_t _1_0_0_1:4;
  163.   uint32_t rs:4;
  164.   uint32_t rn:4;
  165.   uint32_t rd:4;
  166.   uint32_t s:1;
  167.   uint32_t a:1;
  168.   uint32_t  _0_0_0_0_0_0:6;
  169.   uint32_t cond:4;
  170. };
  171. struct arm_mul_long {
  172.   uint32_t rm:4;
  173.   uint32_t _1_0_0_1:4;
  174.   uint32_t rs:4;
  175.   uint32_t rd_lo:4;
  176.   uint32_t rd_hi:4;
  177.   uint32_t s:1;
  178.   uint32_t a:1;
  179.   uint32_t u:1;
  180.   uint32_t  _0_0_0_0_1:5;
  181.   uint32_t cond:4;
  182. };
  183. struct arm_msr_rot_imm32 {
  184.   uint32_t imm8:8;
  185.   uint32_t rotate_imm:4;
  186.   uint32_t sbo:4;
  187.   uint32_t field_c:1;
  188.   uint32_t field_x:1;
  189.   uint32_t field_s:1;
  190.   uint32_t field_f:1;
  191.   uint32_t _1_0:2;
  192.   uint32_t r:1;
  193.   uint32_t _0_0_1_1_0:5;
  194.   uint32_t cond:4;
  195. };
  196. struct arm_msr_reg {
  197.   uint32_t rm:4;
  198.   uint32_t _0_0_0_0:4;
  199.   uint32_t sbz:4;
  200.   uint32_t sbo:4;
  201.   uint32_t field_c:1;
  202.   uint32_t field_x:1;
  203.   uint32_t field_s:1;
  204.   uint32_t field_f:1;
  205.   uint32_t _1_0:2;
  206.   uint32_t r:1;
  207.   uint32_t _0_0_0_1_0:5;
  208.   uint32_t cond:4;
  209. };
  210. struct arm_mrs {
  211.   uint32_t sbz:12;
  212.   uint32_t rd:4;
  213.   uint32_t sbo:4;
  214.   uint32_t _0_0:2;
  215.   uint32_t r:1;
  216.   uint32_t _0_0_0_1_0:5;
  217.   uint32_t cond:4;
  218. };
  219. struct arm_branch {
  220.   uint32_t sign_imm:23;
  221.   uint32_t sign_bit:1;
  222.   uint32_t l:1;
  223.   uint32_t _1_0_1:3;
  224.   uint32_t cond:4;
  225. };
  226. struct arm_branch_exchange {
  227.   uint32_t rm:4;
  228.   uint32_t _0_0_0_1:4;
  229.   uint32_t sbo:12;
  230.   uint32_t _0_0_0_1_0_0_1_0:8;
  231.   uint32_t cond:4;
  232. };
  233. /* =================== THUMB HELPER =================== */
  234. struct thumb_alu {
  235.   uint16_t rd_rn:3;
  236.   uint16_t rm_rs:3;
  237.   uint16_t opcode:4;
  238.   uint16_t _0_1_0_0_0_0:6;
  239. };
  240. struct thumb_branch {
  241.   uint16_t imm10:10;
  242.   uint16_t sign_bit:1;
  243.   uint16_t h:2;
  244.   uint16_t _1_1_1:3;
  245. };
  246.  
  247. #define LSHIFT_RANGE_MASK(rn_mask, shift)\
  248.  ((rn_mask) <<(shift))
  249. #define RSHIFT_RANGE_MASK(rn_mask, shift)\
  250.  ((rn_mask) >>(shift))
  251. #define THUMB_CODE_MASK 0xffffffe
  252. #define ARM7_CODE_MASK 0xffffffc
  253. #define ARM7_MEM_MASK 0xffffffc
  254.  
  255. finline kable
  256. arm7_privilege_mode (struct gba *const agb) {
  257.   const uint32_t mode = agb->arm7.cpsr.mode & 0x0F;
  258.   if (mode != 0)
  259.     return true;
  260.   else
  261.     return false;
  262. }
  263.  
  264. finline
  265. struct psr *arm7_mode_spsr (struct gba *const agb, const uint32_t mode) {
  266.   struct arm7 *const arm = & agb->arm7;
  267.   switch (mode & 0x0F) {
  268.   case ARM7_MODE_USER: return & arm->spsr_t[SPSRb_SYSUSER];
  269.   case ARM7_MODE_SYS: return & arm->spsr_t[SPSRb_SYSUSER];
  270.   case ARM7_MODE_FIQ: return & arm->spsr_t[SPSRb_FIQ];
  271.   case ARM7_MODE_MGR: return & arm->spsr_t[SPSRb_MGR];
  272.   case ARM7_MODE_ABT: return & arm->spsr_t[SPSRb_ABT];
  273.   case ARM7_MODE_UNDEF: return & arm->spsr_t[SPSRb_UDEF];
  274.   case ARM7_MODE_IRQ: return & arm->spsr_t[SPSRb_IRQ];
  275.   default: assert (0); break;
  276.   }
  277.   return null;
  278. }
  279.  
  280. finline
  281. struct psr *arm7_cur_spsr (struct gba *const agb) {
  282.   struct arm7 *const arm = & agb->arm7;
  283.   return arm7_mode_spsr (agb, arm->cpsr.mode);
  284. }
  285.  
  286. finline void                          
  287. arm7_mode_switch (struct gba *const agb, const uint32_t new_mode) {
  288.   struct arm7 *const arm = & agb->arm7;
  289.   const uint32_t mode = arm->cpsr.mode & 0x0F;
  290.   kable saveR8bank = false;
  291.   kable self_fiq = false;
  292.   uint32_t *const regs = & arm->regs[0];
  293.  
  294.   if (    arm7_mode_spsr (agb, new_mode)
  295.       != arm7_cur_spsr (agb) )
  296.   {
  297.       if (mode == ARM7_MODE_FIQ
  298.         || (new_mode & 0x0F) == ARM7_MODE_FIQ)
  299.       {
  300.         saveR8bank = true;
  301.       }
  302.  
  303.       switch (mode & 0x0F) {
  304.       case ARM7_MODE_USER:
  305.       case ARM7_MODE_SYS:
  306.         arm->r1314_t[R1314b_SYSUSER+0] = regs[13];
  307.         arm->r1314_t[R1314b_SYSUSER+1] = regs[14];
  308.         break;
  309.       case ARM7_MODE_MGR:
  310.         arm->r1314_t[R1314b_MGR+0] = regs[13];
  311.         arm->r1314_t[R1314b_MGR+1] = regs[14];
  312.         break;
  313.       case ARM7_MODE_ABT:
  314.         arm->r1314_t[R1314b_ABT+0] = regs[13];
  315.         arm->r1314_t[R1314b_ABT+1] = regs[14];
  316.         break;
  317.       case ARM7_MODE_UNDEF:
  318.         arm->r1314_t[R1314b_UDEF+0] = regs[13];
  319.         arm->r1314_t[R1314b_UDEF+1] = regs[14];
  320.         break;
  321.       case ARM7_MODE_IRQ:
  322.         arm->r1314_t[R1314b_IRQ+0] = regs[13];
  323.         arm->r1314_t[R1314b_IRQ+1] = regs[14];
  324.         break;
  325.       case ARM7_MODE_FIQ:
  326.         arm->r1314_t[R1314b_FIQ+0] = regs[13];
  327.         arm->r1314_t[R1314b_FIQ+1] = regs[14];
  328.         self_fiq = true;
  329.         break;
  330.       default:
  331.         assert (0);
  332.         break;
  333.       }
  334.       if (saveR8bank != false) {
  335.         if (self_fiq != false) {
  336.           arm->r812_t[R812b_FIQ+0] = regs[8];
  337.           arm->r812_t[R812b_FIQ+1] = regs[9];
  338.           arm->r812_t[R812b_FIQ+2] = regs[10];
  339.           arm->r812_t[R812b_FIQ+3] = regs[11];
  340.           arm->r812_t[R812b_FIQ+4] = regs[12];
  341.         } else {
  342.           arm->r812_t[R812b_EXCEPT_FIQ+0] = regs[8];
  343.           arm->r812_t[R812b_EXCEPT_FIQ+1] = regs[9];
  344.           arm->r812_t[R812b_EXCEPT_FIQ+2] = regs[10];
  345.           arm->r812_t[R812b_EXCEPT_FIQ+3] = regs[11];
  346.           arm->r812_t[R812b_EXCEPT_FIQ+4] = regs[12];
  347.         }
  348.       }
  349.  
  350.       switch (new_mode & 0x0F) {
  351.       case ARM7_MODE_USER:
  352.       case ARM7_MODE_SYS:
  353.         regs[13] = arm->r1314_t[R1314b_SYSUSER+0];
  354.         regs[14] = arm->r1314_t[R1314b_SYSUSER+1];
  355.         break;
  356.       case ARM7_MODE_MGR:
  357.         regs[13] = arm->r1314_t[R1314b_MGR+0];
  358.         regs[14] = arm->r1314_t[R1314b_MGR+1];
  359.         break;
  360.       case ARM7_MODE_ABT:
  361.         regs[13] = arm->r1314_t[R1314b_ABT+0];
  362.         regs[14] = arm->r1314_t[R1314b_ABT+1];
  363.         break;
  364.       case ARM7_MODE_UNDEF:
  365.         regs[13] = arm->r1314_t[R1314b_UDEF+0];
  366.         regs[14] = arm->r1314_t[R1314b_UDEF+1];
  367.         break;
  368.       case ARM7_MODE_IRQ:
  369.         regs[13] = arm->r1314_t[R1314b_IRQ+0];
  370.         regs[14] = arm->r1314_t[R1314b_IRQ+1];
  371.         break;
  372.       case ARM7_MODE_FIQ:
  373.         regs[13] = arm->r1314_t[R1314b_FIQ+0];
  374.         regs[14] = arm->r1314_t[R1314b_FIQ+1];
  375.         break;
  376.       default:
  377.         assert (0);
  378.         break;
  379.       }
  380.       if (saveR8bank != false) {
  381.         if (self_fiq == false) {
  382.           regs[8] = arm->r812_t[R812b_FIQ+0];
  383.           regs[9] = arm->r812_t[R812b_FIQ+1];
  384.           regs[10] = arm->r812_t[R812b_FIQ+2];
  385.           regs[11] = arm->r812_t[R812b_FIQ+3];
  386.           regs[12] = arm->r812_t[R812b_FIQ+4];
  387.         } else {
  388.           regs[8] = arm->r812_t[R812b_EXCEPT_FIQ+0];
  389.           regs[9] = arm->r812_t[R812b_EXCEPT_FIQ+1];
  390.           regs[10] = arm->r812_t[R812b_EXCEPT_FIQ+2];
  391.           regs[11] = arm->r812_t[R812b_EXCEPT_FIQ+3];
  392.           regs[12] = arm->r812_t[R812b_EXCEPT_FIQ+4];
  393.         }
  394.       }
  395.   }
  396. }
  397.  
  398. finline void
  399. spsr_to_cpsr (struct gba *const agb) {
  400.   struct psr *spsr = arm7_cur_spsr (agb);
  401.   const uint32_t psrc = spsr->blk;
  402.   arm7_mode_switch (agb, spsr->mode);
  403.   agb->arm7.cpsr.blk = psrc;
  404. }
  405.  
  406. finline
  407. int32_t mul_clks (uint32_t rs_value) {
  408.   /* multiplier's clks, m
  409.    see ARM7TDMI Technical Reference Manual's 6.20 Instruction speed summary
  410.    m is:
  411.    1 if bits [31:8] of the multiplier operand (Rs) are all zero or one, else
  412.    2 if bits [31:16] of the multiplier operand (Rs) are all zero or one, else
  413.    3 if bits [31:24] of the multiplier operand (Rs) are all zero or all one, else
  414.    4. */
  415.          
  416.   if (rs_value & 0x80000000)                                    
  417.     rs_value = ~rs_value;
  418.  
  419.   if ((rs_value & 0xFFFFFF00) == 0)                        
  420.     return 1;                            
  421.   else if ((rs_value & 0xFFFF0000) == 0)                    
  422.     return 2;
  423.   else if ((rs_value & 0xFF000000) == 0)                    
  424.     return 3;                            
  425.   else                                                
  426.     return 4;    
  427. }
  428.  
  429. finline
  430. int32_t isa_arm7_mul (struct gba *const agb,
  431.                                   const uint32_t opcode,
  432.                                   const uint32_t a_bit,
  433.                                   const uint32_t s_bit)
  434. {
  435.   /* 27 26 25 24 23 22 21 20   19 - 16    15 - 12     11 10 9 8    7 6 5 4      3 2 1 0
  436.       0  0  0  0  0  0  A  S      Rd         Rn           Rs       1 0 0 1        Rm       MUL/MLA */
  437.   struct arm7 *const arm = & agb->arm7;
  438.   uint32_t *const regs = & arm->regs[0];
  439.   const struct arm_mul *const m_code = (const struct arm_mul *const) & opcode;
  440.   const uint32_t rs_value = arm->regs[m_code->rs];
  441.  
  442.   if (a_bit != 0) {
  443.     /* MLA instruction */
  444.     const uint32_t output = rs_value * regs[m_code->rm] + regs[m_code->rn];
  445.     arm->regs[m_code->rd] = output;
  446.     if (s_bit != 0) {
  447.       arm->cpsr.c = 0; /* Destroy flag-c */
  448.       arm->cpsr.z = output == 0 ? 1 : 0;
  449.       arm->cpsr.n = output & 0x80000000 ? 1 : 0;
  450.     }
  451.     return mul_clks (rs_value) + 1;
  452.   } else {
  453.     /* MUL instruction */
  454.     const uint32_t output = rs_value * regs[m_code->rm];
  455.     arm->regs[m_code->rd] = output;
  456.     if (s_bit != 0) {
  457.       arm->cpsr.c = 0; /* Destroy flag-c */
  458.       arm->cpsr.z = output == 0 ? 1 : 0;
  459.       arm->cpsr.n = output & 0x80000000 ? 1 : 0;
  460.     }
  461.     return mul_clks (rs_value) + 1 + 1;
  462.   }
  463.   return 0;
  464. }
  465.  
  466. finline
  467. int32_t isa_arm7_mul_long (struct gba *const agb,
  468.                                        const uint32_t opcode,
  469.                                        const uint32_t u_bit,
  470.                                        const uint32_t a_bit,
  471.                                        const uint32_t s_bit)
  472. {
  473.   /* 27 26 25 24 23 22 21 20   19 - 16    15 - 12     11 10 9 8    7 6 5 4      3 2 1 0
  474.       0  0  0  0  1  U  A  S    RdHi        RdLo          Rs       1 0 0 1        Rm       UMULL/UMLAL/SMULL/SMLAL */
  475.   struct arm7 *const arm = & agb->arm7;
  476.   uint32_t *const regs = & arm->regs[0];
  477.   const struct arm_mul_long *const m_code = (const struct arm_mul_long *const) & opcode;
  478.   const uint32_t rs_value = arm->regs[m_code->rs];
  479.  
  480.   if (a_bit != 0) {
  481.     if (u_bit == 0) {
  482.       /* UMLAL instruction */
  483.       const uint64_t rs_value_u64 = rs_value;
  484.       const uint64_t rm_value_u64 = regs[m_code->rm];
  485.       const uint64_t rd_lo_value_u64 = regs[m_code->rd_lo];
  486.       const uint64_t rd_hi_value_u64 = regs[m_code->rd_hi];
  487.       const uint64_t output = rs_value_u64 * rm_value_u64 + (( rd_hi_value_u64 << 32) | rd_lo_value_u64);
  488.       regs[m_code->rd_lo] = * (uint32_t *) & output;
  489.       regs[m_code->rd_hi] = ((uint32_t *) & output) [1];
  490.       if (s_bit != 0) {
  491.         arm->cpsr.v = 0; /* Destroy flag-v ?? */
  492.         arm->cpsr.c = 0; /* Destroy flag-c */
  493.         arm->cpsr.z = output == 0 ? 1 : 0;
  494.         arm->cpsr.n = ((uint32_t *) & output) [1] & LSHIFT_RANGE_MASK (1, 31) ? 1 : 0;
  495.       }
  496.     } else {
  497.       /* SMLAL instruction */
  498.       const int32_t rs_value_s32 = rs_value;
  499.       const int64_t rs_value_s64 = rs_value_s32;
  500.       const int32_t rm_value_s32 = regs[m_code->rm];
  501.       const int64_t rm_value_s64 = rm_value_s32;
  502.       const uint64_t rd_lo_value_u64 = regs[m_code->rd_lo];
  503.       const uint64_t rd_hi_value_u64 = regs[m_code->rd_hi];
  504.       const uint64_t output = rs_value_s64 * rm_value_s64 + (( rd_hi_value_u64 << 32) | rd_lo_value_u64);
  505.       regs[m_code->rd_lo] = * (uint32_t *) & output;
  506.       regs[m_code->rd_hi] = ((uint32_t *) & output) [1];
  507.       if (s_bit != 0) {
  508.         arm->cpsr.v = 0; /* Destroy flag-v ?? */
  509.         arm->cpsr.c = 0; /* Destroy flag-c */
  510.         arm->cpsr.z = output == 0 ? 1 : 0;
  511.         arm->cpsr.n = ((uint32_t *) & output) [1] & LSHIFT_RANGE_MASK (1, 31) ? 1 : 0;
  512.       }
  513.     }
  514.     return mul_clks (rs_value) + 1 + 2;
  515.   } else {
  516.     if (u_bit == 0) {
  517.       /* UMULL instruction */
  518.       const uint64_t rs_value_u64 = rs_value;
  519.       const uint64_t rm_value_u64 = regs[m_code->rm];
  520.       const uint64_t output = rs_value_u64 * rm_value_u64;
  521.       regs[m_code->rd_lo] = * (uint32_t *) & output;
  522.       regs[m_code->rd_hi] = ((uint32_t *) & output) [1];
  523.       if (s_bit != 0) {
  524.         arm->cpsr.v = 0; /* Destroy flag-v ?? */
  525.         arm->cpsr.c = 0; /* Destroy flag-c */
  526.         arm->cpsr.z = output == 0 ? 1 : 0;
  527.         arm->cpsr.n = ((uint32_t *) & output) [1] & LSHIFT_RANGE_MASK (1, 31) ? 1 : 0;
  528.       }
  529.     } else {
  530.       /* SMULL instruction */
  531.       const int32_t rs_value_s32 = rs_value;
  532.       const int64_t rs_value_s64 = rs_value_s32;
  533.       const int32_t rm_value_s32 = regs[m_code->rm];
  534.       const int64_t rm_value_s64 = rm_value_s32;
  535.       const int64_t output = rs_value_s64 * rm_value_s64;
  536.       regs[m_code->rd_lo] = * (uint32_t *) & output;
  537.       regs[m_code->rd_hi] = ((uint32_t *) & output) [1];
  538.       if (s_bit != 0) {
  539.         arm->cpsr.v = 0; /* Destroy flag-v ?? */
  540.         arm->cpsr.c = 0; /* Destroy flag-c */
  541.         arm->cpsr.z = output == 0 ? 1 : 0;
  542.         arm->cpsr.n = ((uint32_t *) & output) [1] & LSHIFT_RANGE_MASK (1, 31) ? 1 : 0;
  543.       }
  544.     }
  545.     return mul_clks (rs_value) + 1 + 1;
  546.   }
  547.   return 0;
  548. }
  549.  
  550. finline
  551. int32_t isa_arm7_atomic_swap (struct gba *const agb,
  552.                                   const uint32_t opcode,
  553.                                   const uint32_t b_bit)
  554. {
  555.   /* 27 26 25 24 23 22 21 20   19 - 16    15 - 12     11 10 9 8    7 6 5 4   3 2 1 0
  556.       0  0  0  1  0  B  0  0      Rn         Rd        0  0 0 0    1 0 0 1     Rm    SWP/SWPB */
  557.   struct arm7 *const arm = & agb->arm7;
  558.   uint32_t *const regs = & arm->regs[0];
  559.   const struct arm_atomic_memory_access *const m_code = (const struct arm_atomic_memory_access *const) & opcode;
  560.  
  561.   if (b_bit != 0) {
  562.     /* SWPB instruction */
  563.     uint8_t memory;
  564.     const int32_t wait_state = agb_mbus_rb (agb, regs[m_code->rn], & memory, false)
  565.                                          +  agb_mbus_wb (agb, regs[m_code->rn], regs[m_code->rm], false) + 4;
  566.     regs[m_code->rd] = memory;
  567.     return wait_state;
  568.   } else {
  569.     /* SWP instruction */
  570.     uint32_t memory;
  571.     const uint32_t rn_address = regs[m_code->rn];
  572.     const uint32_t rn_rorate = (rn_address & 3) << 3;
  573.     const int32_t wait_state = agb_mbus_rw (agb, rn_address, & memory, false)
  574.                                          +  agb_mbus_ww (agb, rn_address, regs[m_code->rm], false) + 4;
  575.     if (rn_rorate != 0)
  576.       regs[m_code->rd] = memory >> rn_rorate | memory << 32 - rn_rorate;
  577.     else
  578.       regs[m_code->rd] = memory;
  579.     return wait_state;
  580.   }
  581.   return 0;
  582. }
  583.  
  584. finline
  585. int32_t isa_arm7_memory_access_sbh_base (struct gba *const agb,
  586.                                   const uint32_t p,
  587.                                   const uint32_t u,
  588.                                   const uint32_t w,
  589.                                   const uint32_t l,
  590.                                   const uint32_t s,
  591.                                   const uint32_t h,
  592.                                   const uint32_t rn,
  593.                                   const uint32_t rd,
  594.                                   const uint32_t rhs)
  595. {
  596.   struct arm7 *const arm = & agb->arm7;
  597.   uint32_t *const regs = & arm->regs[0];
  598.   int32_t wait_state;
  599.   uint32_t rn_writeback;
  600.   uint32_t rn_address;
  601.  
  602.   if (u != 0)
  603.     rn_writeback = regs[rn] + rhs;
  604.   else
  605.     rn_writeback = regs[rn] - rhs;
  606.  
  607.   if (p != 0)
  608.     rn_address = rn_writeback;
  609.   else
  610.     rn_address = regs[rn];
  611.  
  612.   assert ( (l == 0 && s == 0 && h != 0) /* STRH instruction 0, 0, 1 */
  613.     || (l != 0 && s == 0 && h != 0) /* LDRH instruction 1, 0, 1*/
  614.     || (l != 0 && s != 0 && h == 0) /* LDRSB instruction 1, 1, 0*/
  615.     || (l != 0 && s != 0 && h != 0) ); /* LDRSH instruction 1, 1, 1 */
  616.  
  617.   if (l == 0 && s == 0 && h != 0) {
  618.     /* STRH instruction */
  619.     wait_state = agb_mbus_whw ( agb, rn_address,  regs[rd], false) + 2;
  620.     if ( (w != 0 || p == 0))
  621.       regs[rn] = rn_writeback;
  622.   }
  623.   if (l != 0 && s == 0 && h != 0) {
  624.     /* LDRH instruction */
  625.     uint32_t memory;
  626.  
  627.     wait_state = agb_mbus_rhw ( agb, rn_address,
  628.                                    (uint16_t *)& memory, false) + 3;
  629.     memory &= 0xFFFF;
  630.  
  631.     if (rn_address & 1)
  632.       regs[rd] = memory >> 8 | memory << 24;
  633.     else
  634.       regs[rd] = memory;
  635.  
  636.     if (     (w != 0 || p == 0)
  637.       && rd != rn)
  638.       regs[rn] = rn_writeback;
  639.   }
  640.   if (l != 0 && s != 0 && h == 0) {
  641.     /* LDRSB instruction */
  642.     int8_t memory;
  643.  
  644.     wait_state = agb_mbus_rb ( agb, rn_address,
  645.                                  (uint8_t *) & memory, false) + 3;
  646.     *(int32_t *)& regs[rd] = memory;
  647.  
  648.     if (     (w != 0 || p == 0)
  649.       && rd != rn)
  650.       regs[rn] = rn_writeback;
  651.   }
  652.   if (l != 0 && s != 0 && h != 0) {
  653.     /* LDRSH instruction */
  654.     int16_t memory;
  655.  
  656.     wait_state = agb_mbus_rhw ( agb, rn_address,
  657.                                    (uint16_t *)& memory, false) + 3;
  658.     if (rn_address & 1)
  659.       * (int32_t *)& regs[rd] = ((int8_t *)& memory)[1];
  660.     else
  661.        * (int32_t *)& regs[rd] = memory;
  662.  
  663.     if (     (w != 0 || p == 0)
  664.       && rd != rn)
  665.       regs[rn] = rn_writeback;
  666.   }
  667.   return wait_state;
  668. }
  669.  
  670. finline
  671. int32_t isa_arm7_memory_access_sbh_pad_imm8 (struct gba *const agb,
  672.                                   const uint32_t opcode,
  673.                                   const uint32_t p,
  674.                                   const uint32_t u,
  675.                                   const uint32_t w,
  676.                                   const uint32_t l,
  677.                                   const uint32_t s,
  678.                                   const uint32_t h)
  679. {
  680.   /* 27 26 25 24 23 22 21 20   19 - 16    15 - 12    11 10 9 8   7 6 5 4   3 2 1 0
  681.       0  0  0  P  U  1  W  L     Rn          Rd       Offset1    1 S H 1   Offset2    LDRH/STRH/LDRSB/LDRSH Imm8 */
  682.   struct arm7 *const arm = & agb->arm7;
  683.   uint32_t *const regs = & arm->regs[0];
  684.   const struct arm_memory_access_sbh_imm8 *const m_code = (const struct arm_memory_access_sbh_imm8 *const) & opcode;
  685.   const uint32_t pad =(m_code->imm_l + (m_code->imm_h << 4));
  686.   return isa_arm7_memory_access_sbh_base (agb, p, u, w, l, s, h, m_code->rn, m_code->rd, pad);
  687. }
  688.  
  689. finline
  690. int32_t isa_arm7_memory_access_sbh_reg (struct gba *const agb,
  691.                                   const uint32_t opcode,
  692.                                   const uint32_t p,
  693.                                   const uint32_t u,
  694.                                   const uint32_t w,
  695.                                   const uint32_t l,
  696.                                   const uint32_t s,
  697.                                   const uint32_t h)
  698. {
  699.   /* 27 26 25 24 23 22 21 20   19 - 16    15 - 12    11 10 9 8   7 6 5 4   3 2 1 0
  700.       0  0  0  P  U  0  W  L       Rn        Rd       0  0 0 0   1 S H 1     Rm     LDRH/STRH/LDRSB/LDRSH Register */
  701.   struct arm7 *const arm = & agb->arm7;
  702.   uint32_t *const regs = & arm->regs[0];
  703.   const struct arm_memory_access_sbh_reg *const m_code = (const struct arm_memory_access_sbh_reg *const) & opcode;
  704.   return isa_arm7_memory_access_sbh_base (agb, p, u, w, l, s, h, m_code->rn, m_code->rd, regs[m_code->rm]);
  705. }
  706.  
  707. finline
  708. int32_t isa_arm7_branch_exchange (struct gba *const agb,
  709.                                   const uint32_t opcode)
  710. {
  711.   /* 27 26 25 24 23 22 21 20  19 - 16    15 - 12    11 10 9 8   7 6 5 4   3 2 1 0
  712.       0  0  0  1  0  0  1  0  1 1 1 1    1 1 1 1     1  1 1 1   0 0 0 1     Rn     BX */
  713.   struct arm7 *const arm = & agb->arm7;
  714.   uint32_t *const regs = & arm->regs[0];
  715.   const struct arm_branch_exchange *const m_code = (const struct arm_branch_exchange *const) & opcode;
  716.   const uint32_t rm_value = regs[m_code->rm];
  717.  
  718.   if (rm_value & 1) {
  719.     /* to thumb mode, flush thumb pipeline */
  720.     regs[15] = rm_value & THUMB_CODE_MASK;
  721.     arm->cpsr.thumb = 1;
  722.     return thumb_flush (agb) + 3;
  723.   } else {
  724.     /* to arm7 mode, flush arm7 pipeline  */
  725.     regs[15] = rm_value & ARM7_CODE_MASK;
  726.     arm->cpsr.thumb = 0;
  727.     return arm7_flush (agb) + 3;
  728.   }
  729.   return 0;
  730. }
  731.    
  732. finline
  733. uint32_t arm7_alu_helper_rot_imm32 (uint32_t imm8, uint32_t shift_even, uint32_t *const carry) {
  734.   if (shift_even == 0)
  735.     return imm8;
  736.   else {
  737.     if (carry == null) {
  738.       const uint32_t shift = shift_even << 1;
  739.       return imm8 >> shift | imm8 << 32 - shift;
  740.     } else {
  741.       const uint32_t shift = shift_even << 1;
  742.       const uint32_t imm32 = imm8 >> shift | imm8 << 32 - shift;
  743.       if (imm32 & LSHIFT_RANGE_MASK (1, 31))
  744.         * carry = 1;
  745.       else
  746.         * carry = 0;
  747.       return imm32;
  748.     }
  749.   }
  750. }
  751.  
  752. finline
  753. uint32_t arm7_alu_shift_imm5 (struct arm7 *const arm, uint32_t rm /* value */, const uint32_t shift, const uint32_t imm5, uint32_t *const carry) {
  754.   if (carry != null) {
  755.     if (shift == 0) {
  756.       /* shift - lsl */
  757.       if (imm5 != 0)
  758.         *carry = rm & LSHIFT_RANGE_MASK (1, 32 - imm5) ? 1 : 0;
  759.       return rm << imm5;
  760.     } else if (shift == 1) {
  761.       /* shift - lsr */
  762.       if (imm5 == 0) {
  763.         *carry = rm & LSHIFT_RANGE_MASK (1, 31) ? 1 : 0;
  764.         return 0;
  765.       } else {
  766.         *carry = rm & LSHIFT_RANGE_MASK (1, imm5 - 1) ? 1 : 0;
  767.         return rm >> imm5;
  768.       }
  769.     } else if (shift ==2) {
  770.       /* shift - asr */
  771.       if (imm5 == 0) {
  772.         if (rm & LSHIFT_RANGE_MASK (1, 31)) {
  773.           *carry = 1;
  774.           return 0xFFFFFFFF;
  775.         } else {
  776.           *carry = 0;
  777.           return 0;
  778.         }
  779.       } else {
  780.         *carry = rm & LSHIFT_RANGE_MASK (1, imm5 - 1) ? 1 : 0;
  781.         return (int32_t) rm >> imm5;
  782.       }
  783.     } else if (shift == 3) {
  784.       /* shift - ror */
  785.       if (imm5 == 0) {
  786.         /* shift - rrx */
  787.         *carry = rm & LSHIFT_RANGE_MASK (1, 0) ? 1 : 0;
  788.         return rm >> 1 | (arm->cpsr.c ? LSHIFT_RANGE_MASK (1, 31) : 0);
  789.       } else {
  790.         *carry = rm & LSHIFT_RANGE_MASK (1, imm5 - 1) ? 1 : 0;
  791.         return rm >> imm5 | rm << 32 - imm5;
  792.       }
  793.     } else {
  794.       assert (0);
  795.     }
  796.   } else {
  797.     if (shift == 0) {
  798.       /* shift - lsl */
  799.       return rm << imm5;
  800.     } else if (shift == 1) {
  801.       /* shift - lsr */
  802.       if (imm5 == 0)
  803.         return 0;
  804.       else
  805.         return rm >> imm5;
  806.     } else if (shift ==2) {
  807.       /* shift - asr */
  808.       if (imm5 == 0)
  809.         if (rm & LSHIFT_RANGE_MASK (1, 31))
  810.           return 0xFFFFFFFF;
  811.         else
  812.           return 0;
  813.       else
  814.         return (int32_t) rm >> imm5;
  815.     } else if (shift == 3) {
  816.       /* shift - ror */
  817.       if (imm5 == 0) {
  818.         /* shift - rrx */
  819.         return rm >> 1 | (arm->cpsr.c != 0 ? LSHIFT_RANGE_MASK (1, 31) : 0);
  820.       } else {
  821.         return rm >> imm5 | rm << 32 - imm5;
  822.       }
  823.     } else {
  824.       assert (0);
  825.     }
  826.   }
  827.   assert (0);
  828.   return 0;
  829. }
  830.  
  831. finline
  832. uint32_t arm7_alu_shift_rs (struct arm7 *const arm, uint32_t rm /* value */, const uint32_t shift, const uint32_t rs /* value */, uint32_t *const carry) {
  833.   const uint32_t rs_8bit = rs & 0xFF;
  834.   if (rs_8bit == 0)
  835.     return rm;
  836.   else {
  837.     if (carry == null) {
  838.       if (shift == 0) {
  839.         /* shift - lsl */
  840.         if (rs_8bit < 32)
  841.           return rm << rs_8bit;
  842.         else if (rs_8bit == 32)
  843.           return 0;
  844.         else
  845.           return 0;
  846.       } else if (shift == 1) {
  847.         /* shift - lsr */
  848.         if (rs_8bit < 32)
  849.           return rm >> rs_8bit;
  850.         else if (rs_8bit == 32)
  851.           return 0;
  852.         else
  853.           return 0;
  854.       } else if (shift ==2) {
  855.         /* shift - asr */
  856.         if (rs_8bit < 32)
  857.           return (int32_t) rm >> rs_8bit;
  858.         else if (rs_8bit >= 32)
  859.           if (rm & LSHIFT_RANGE_MASK (1, 31))
  860.             return 0xFFFFFFFF;
  861.           else
  862.             return 0;
  863.       } else if (shift == 3) {
  864.         /* shift - ror */
  865.         if ( (rs_8bit & 31) == 0)
  866.           return rm;
  867.         else
  868.           return rm >> (rs_8bit & 31) | rm << 32 - (rs_8bit & 31);
  869.       } else {
  870.         assert (0);
  871.       }
  872.     } else {
  873.       if (shift == 0) {
  874.         /* shift - lsl */
  875.         if (rs_8bit < 32) {
  876.           * carry = rm & LSHIFT_RANGE_MASK (1, 32 - rs_8bit) ? 1 : 0;
  877.           return rm << rs_8bit;
  878.         } else if (rs_8bit == 32) {
  879.           * carry = rm & 1;
  880.           return 0;
  881.         } else {
  882.           * carry = 0;
  883.           return 0;
  884.         }
  885.       } else if (shift == 1) {
  886.         /* shift - lsr */
  887.         if (rs_8bit < 32) {
  888.           * carry = rm & LSHIFT_RANGE_MASK (1, rs_8bit - 1) ? 1 : 0;
  889.           return rm >> rs_8bit;
  890.         } else if (rs_8bit == 32) {
  891.           * carry = rm & LSHIFT_RANGE_MASK (1, 31) ? 1 : 0;
  892.           return 0;
  893.         } else {
  894.           * carry = 0;
  895.           return 0;
  896.         }
  897.       } else if (shift ==2) {
  898.         /* shift - asr */
  899.         if (rs_8bit < 32) {
  900.           * carry = rm & LSHIFT_RANGE_MASK (1, rs_8bit - 1) ? 1 : 0;
  901.           return (int32_t) rm >> rs_8bit;
  902.         } else if (rs_8bit >= 32) {
  903.           if (rm & LSHIFT_RANGE_MASK (1, 31)) {
  904.             * carry = 1;
  905.             return 0xFFFFFFFF;
  906.           } else {
  907.             * carry = 0;
  908.             return 0;
  909.           }
  910.         }
  911.       } else if (shift == 3) {
  912.         /* shift - ror */
  913.         if ( (rs_8bit & 31) == 0) {
  914.           * carry = rm & LSHIFT_RANGE_MASK (1, 31) ? 1 : 0;
  915.           return rm;
  916.         } else {
  917.            * carry = rm & LSHIFT_RANGE_MASK (1, (rs_8bit & 31) - 1) ? 1 : 0;
  918.           return rm >> (rs_8bit & 31) | rm << 32 - (rs_8bit & 31);
  919.         }
  920.       } else {
  921.         assert (0);
  922.       }
  923.     }
  924.   }
  925.   assert (0);
  926.   return 0;
  927. }
  928.  
  929. /* ============================ ARM7 Rotate imm32 alu ============================== */
  930.  
  931. finline  int32_t
  932. isa_arm7_alu_rot_imm32 (struct gba *const agb,
  933.                                   const uint32_t opcode,
  934.                                   const kable  update_rd,
  935.                                   uint32_t (*const alu_operate) (const uint32_t rn, const uint32_t oprand2, const uint32_t carry, uint32_t *const output_ext),
  936.                                   void (*const update_flags) (struct arm7 *const arm,
  937.                                       const uint32_t shift_c,
  938.                                       const uint32_t output,
  939.                                       const uint32_t output_ext,
  940.                                       const uint32_t sop_lhs,
  941.                                       const uint32_t sop_rhs),
  942.                                   const uint32_t s_bit)
  943. {
  944.   struct arm7 *const arm = & agb->arm7;
  945.   uint32_t *const regs = & arm->regs[0];
  946.   const struct arm_alu_rot_imm32 *const m_code = (const struct arm_alu_rot_imm32 *const) & opcode;
  947.         uint32_t output_ext;
  948.   uint32_t shift_c = arm->cpsr.c;
  949.   const uint32_t rhs = arm7_alu_helper_rot_imm32 (m_code->immed_8, m_code->rorate_imm, s_bit != 0 ? & shift_c : null);
  950.   const uint32_t lhs = regs[m_code->rn];
  951.   const uint32_t output = alu_operate (lhs, rhs, arm->cpsr.c, & output_ext);
  952.  
  953.   if (update_rd != false) {
  954.     regs[m_code->rd] = output;
  955.   }
  956.   if (s_bit != 0) {
  957.     if (m_code->rd == 15) {
  958.       /* flush pipeline, switch cpu mode */
  959.       spsr_to_cpsr (agb);
  960.       if (arm->cpsr.thumb != 0) {
  961.         /* FIMXE: internal adjust pc only for arm7 */
  962.         const uint32_t pc = regs[15];
  963.         const int32_t wait_state = thumb_flush (agb) + 3;
  964.         regs[15] = pc;
  965.         return wait_state;
  966.       }
  967.       else
  968.         return arm7_flush (agb) + 3;
  969.     } else {
  970.       update_flags (arm, shift_c, output, output_ext, lhs, rhs);
  971.       return 1;
  972.     }
  973.   } else {
  974.     if (m_code->rd != 15)
  975.       return 1;
  976.     else
  977.       return arm7_flush (agb) + 3;
  978.   }
  979.   return 0;
  980. }
  981.  
  982. /* ============================ ARM7 Shift imm5 alu ============================== */
  983.  
  984. finline  int32_t
  985. isa_arm7_alu_shift_imm5 (struct gba *const agb,
  986.                                   const uint32_t opcode,
  987.                                   const uint32_t shift,
  988.                                   const kable  update_rd,
  989.                                   uint32_t (*const alu_operate) (const uint32_t rn, const uint32_t oprand2, const uint32_t carry, uint32_t *const output_ext),
  990.                                   void (*const update_flags) (struct arm7 *const arm,
  991.                                       const uint32_t shift_c,
  992.                                       const uint32_t output,
  993.                                       const uint32_t output_ext,
  994.                                       const uint32_t sop_lhs,
  995.                                       const uint32_t sop_rhs),
  996.                                   const uint32_t s_bit)
  997. {
  998.   struct arm7 *const arm = & agb->arm7;
  999.   uint32_t *const regs = & arm->regs[0];
  1000.   const struct arm_alu_shift_imm5 *const m_code = (const struct arm_alu_shift_imm5 *const) & opcode;
  1001.         uint32_t output_ext;
  1002.   uint32_t shift_c = arm->cpsr.c;
  1003.   const uint32_t rhs = arm7_alu_shift_imm5 (arm, regs[m_code->rm], shift, m_code->shift_imm, s_bit != 0 ? & shift_c : null);
  1004.   const uint32_t lhs = regs[m_code->rn];
  1005.   const uint32_t output = alu_operate (lhs, rhs, arm->cpsr.c, & output_ext);
  1006.  
  1007.   if (update_rd != false) {
  1008.     regs[m_code->rd] = output;
  1009.   }
  1010.   if (s_bit != 0) {
  1011.     if (m_code->rd == 15) {
  1012.       /* flush pipeline, switch cpu mode */
  1013.       spsr_to_cpsr (agb);
  1014.       if (arm->cpsr.thumb != 0) {
  1015.         /* FIMXE: internal adjust pc only for arm7 */
  1016.         const uint32_t pc = regs[15];
  1017.         const int32_t wait_state = thumb_flush (agb) + 3;
  1018.         regs[15] = pc;
  1019.         return wait_state;
  1020.       }
  1021.       else
  1022.         return arm7_flush (agb) + 3;
  1023.     } else {
  1024.       update_flags (arm, shift_c, output, output_ext, lhs, rhs);
  1025.       return 1;
  1026.     }
  1027.   } else {
  1028.     if (m_code->rd != 15)
  1029.       return 1;
  1030.     else
  1031.       return arm7_flush (agb) + 3;
  1032.   }
  1033.   return 0;
  1034. }
  1035.  
  1036. /* ============================ ARM7 Shift rs alu ============================== */
  1037.  
  1038. finline  int32_t
  1039. isa_arm7_alu_shift_rs (struct gba *const agb,
  1040.                                   const uint32_t opcode,
  1041.                                   const uint32_t shift,
  1042.                                   const kable  update_rd,
  1043.                                   uint32_t (*const alu_operate) (const uint32_t rn, const uint32_t oprand2, const uint32_t carry, uint32_t *const output_ext),
  1044.                                   void (*const update_flags) (struct arm7 *const arm,
  1045.                                       const uint32_t shift_c,
  1046.                                       const uint32_t output,
  1047.                                       const uint32_t output_ext,
  1048.                                       const uint32_t sop_lhs,
  1049.                                       const uint32_t sop_rhs),
  1050.                                   const uint32_t s_bit)
  1051. {
  1052.   struct arm7 *const arm = & agb->arm7;
  1053.   uint32_t *const regs = & arm->regs[0];
  1054.   const struct arm_alu_shift_rs *const m_code = (const struct arm_alu_shift_rs *const) & opcode;
  1055.         uint32_t output_ext;
  1056.   uint32_t shift_c = arm->cpsr.c;
  1057.   const uint32_t rhs = arm7_alu_shift_rs (arm, m_code->rm == 15 ? regs[m_code->rm] + 4 : regs[m_code->rm], shift, regs[m_code->rs], s_bit != 0 ? & shift_c : null);
  1058.   const uint32_t lhs = m_code->rn == 15 ? regs[m_code->rn] + 4 : regs[m_code->rn];
  1059.   const uint32_t output = alu_operate (lhs, rhs, arm->cpsr.c, & output_ext);
  1060.  
  1061.   if (update_rd != false) {
  1062.     regs[m_code->rd] = output;
  1063.   }
  1064.   if (s_bit != 0) {
  1065.     if (m_code->rd == 15) {
  1066.       /* flush pipeline, switch cpu mode */
  1067.       spsr_to_cpsr (agb);
  1068.       if (arm->cpsr.thumb != 0) {
  1069.         /* FIMXE: internal adjust pc only for arm7 */
  1070.         const uint32_t pc = regs[15];
  1071.         const int32_t wait_state = thumb_flush (agb) + 3;
  1072.         regs[15] = pc;
  1073.         return wait_state;
  1074.       }
  1075.       else
  1076.         return arm7_flush (agb) + 3;
  1077.     } else {
  1078.       update_flags (arm, shift_c, output, output_ext, lhs, rhs);
  1079.       return 2;
  1080.     }
  1081.   } else {
  1082.     if (m_code->rd != 15)
  1083.       return 2;
  1084.     else
  1085.       return arm7_flush (agb) + 4;
  1086.   }
  1087.   return 0;
  1088. }
  1089.  
  1090. /* ============================ ARM7 operate main ============================== */
  1091. finline uint32_t alu_and (const uint32_t rn, const uint32_t oprand2, const uint32_t carry, uint32_t *const output_ext) { return rn &  oprand2; }
  1092. finline uint32_t alu_eor (const uint32_t rn, const uint32_t oprand2, const uint32_t carry, uint32_t *const output_ext) { return rn ^  oprand2; }
  1093. finline uint32_t alu_orr (const uint32_t rn, const uint32_t oprand2, const uint32_t carry, uint32_t *const output_ext) { return rn |  oprand2; }
  1094. finline uint32_t alu_mov (const uint32_t rn, const uint32_t oprand2, const uint32_t carry, uint32_t *const output_ext) { return       oprand2; }
  1095. finline uint32_t alu_mvn (const uint32_t rn, const uint32_t oprand2, const uint32_t carry, uint32_t *const output_ext) { return      ~oprand2; }
  1096. finline uint32_t alu_bic (const uint32_t rn, const uint32_t oprand2, const uint32_t carry, uint32_t *const output_ext) { return rn & ~oprand2; }
  1097.  
  1098. finline
  1099. uint32_t alu_add (const uint32_t rn, const uint32_t oprand2, const uint32_t carry, uint32_t *const output_ext) {
  1100.   uint64_t output = (uint64_t) rn + (uint64_t) oprand2;
  1101.   assert (output_ext != null);
  1102.  
  1103.   if (output_ext != null)
  1104.     * output_ext = * (((uint32_t *)& output) + 1);
  1105.   return (uint32_t) output;
  1106. }
  1107.  
  1108. finline
  1109. uint32_t alu_adc (const uint32_t rn, const uint32_t oprand2, const uint32_t carry, uint32_t *const output_ext) {
  1110.   uint64_t output = (uint64_t) rn + (uint64_t) oprand2 + (carry == 0 ? 0 : 1);;
  1111.   assert (output_ext != null);
  1112.  
  1113.   if (output_ext != null)
  1114.     * output_ext = * (((uint32_t *)& output) + 1);
  1115.   return (uint32_t) output;
  1116. }
  1117.  
  1118. finline
  1119. uint32_t alu_sub (const uint32_t rn, const uint32_t oprand2, const uint32_t carry, uint32_t *const output_ext) {
  1120.   uint64_t output = (uint64_t) rn - (uint64_t) oprand2;
  1121.   assert (output_ext != null);
  1122.  
  1123.   if (output_ext != null)
  1124.     * output_ext = * (((uint32_t *)& output) + 1);
  1125.   return (uint32_t) output;
  1126. }
  1127.  
  1128. finline
  1129. uint32_t alu_sbc (const uint32_t rn, const uint32_t oprand2, const uint32_t carry, uint32_t *const output_ext) {
  1130.   uint64_t output = (uint64_t) rn - (uint64_t) oprand2 - (carry != 0 ? 0 : 1);
  1131.   assert (output_ext != null);
  1132.  
  1133.   if (output_ext != null)
  1134.     * output_ext = * (((uint32_t *)& output) + 1);
  1135.   return (uint32_t) output;
  1136. }
  1137.  
  1138. finline
  1139. uint32_t alu_rsb (const uint32_t rn, const uint32_t oprand2, const uint32_t carry, uint32_t *const output_ext) {
  1140.   uint64_t output = (uint64_t) oprand2 - (uint64_t) rn;
  1141.   assert (output_ext != null);
  1142.  
  1143.   if (output_ext != null)
  1144.     * output_ext = * (((uint32_t *)& output) + 1);
  1145.   return (uint32_t) output;
  1146. }
  1147.  
  1148. finline
  1149. uint32_t alu_rsc (const uint32_t rn, const uint32_t oprand2, const uint32_t carry, uint32_t *const output_ext) {
  1150.   uint64_t output = (uint64_t) oprand2 - (uint64_t) rn - (carry != 0 ? 0 : 1);
  1151.   assert (output_ext != null);
  1152.  
  1153.   if (output_ext != null)
  1154.     * output_ext = * (((uint32_t *)& output) + 1);
  1155.   return (uint32_t) output;
  1156. }
  1157.  
  1158. /* ============================ ARM7 update flags main ============================== */
  1159. finline
  1160. void update_flags_logic_fast (struct arm7 *const arm, const uint32_t output) {
  1161.  
  1162.   arm->cpsr.n = output & LSHIFT_RANGE_MASK (1, 31) ? 1 : 0;
  1163.   arm->cpsr.z = output == 0 ? 1 : 0;
  1164. }
  1165.  
  1166. finline
  1167. void update_flags_logic (struct arm7 *const arm,
  1168.                                       const uint32_t shift_c,
  1169.                                       const uint32_t output,
  1170.                                       const uint32_t output_ext,
  1171.                                       const uint32_t sop_lhs,
  1172.                                       const uint32_t sop_rhs) {
  1173.  
  1174.   arm->cpsr.n = output & LSHIFT_RANGE_MASK (1, 31) ? 1 : 0;
  1175.   arm->cpsr.z = output == 0 ? 1 : 0;
  1176.   arm->cpsr.c = shift_c;
  1177. }
  1178.  
  1179. finline
  1180. void update_flags_add (struct arm7 *const arm,
  1181.                                       const uint32_t shift_c,
  1182.                                       const uint32_t output,
  1183.                                       const uint32_t output_ext,
  1184.                                       const uint32_t sop_lhs,
  1185.                                       const uint32_t sop_rhs) {
  1186.  
  1187.   const uint32_t v_flag = (!((sop_lhs ^ sop_rhs) & LSHIFT_RANGE_MASK (1, 31)) && ((sop_lhs ^ output) & LSHIFT_RANGE_MASK (1, 31)));
  1188.  
  1189.   arm->cpsr.n = output & LSHIFT_RANGE_MASK (1, 31) ? 1 : 0;
  1190.   arm->cpsr.z = output == 0 ? 1 : 0;
  1191.   arm->cpsr.c = output_ext != 0 ? 1 : 0;
  1192.   arm->cpsr.v = v_flag != 0 ? 1 : 0;
  1193. }
  1194.  
  1195. finline
  1196. void update_flags_sub (struct arm7 *const arm,
  1197.                                       const uint32_t shift_c,
  1198.                                       const uint32_t output,
  1199.                                       const uint32_t output_ext,
  1200.                                       const uint32_t sop_lhs,
  1201.                                       const uint32_t sop_rhs) {
  1202.  
  1203.   const uint32_t v_flag = (((sop_lhs ^ output) & LSHIFT_RANGE_MASK (1, 31)) && ((sop_lhs ^ sop_rhs) & LSHIFT_RANGE_MASK (1, 31)));
  1204.  
  1205.   arm->cpsr.n = output & LSHIFT_RANGE_MASK (1, 31) ? 1 : 0;
  1206.   arm->cpsr.z = output == 0 ? 1 : 0;
  1207.   arm->cpsr.c = output_ext == 0 ? 1 : 0;
  1208.   arm->cpsr.v = v_flag != 0 ? 1 : 0;
  1209. }
  1210.  
  1211. /* ============================ ARM7 alu unwind ============================== */
  1212.  
  1213. finline
  1214. int32_t isa_arm7_psr_load (struct gba *const agb,
  1215.                                   const uint32_t opcode)
  1216. {
  1217.   struct arm7 *const arm = & agb->arm7;
  1218.   uint32_t *const regs = & arm->regs[0];
  1219.   const struct arm_mrs *const m_code = (const struct arm_mrs *const) & opcode;
  1220.   assert (m_code->rd != 15);
  1221.   if (m_code->r != 0)
  1222.     regs[m_code->rd] = arm7_cur_spsr (agb)->blk;
  1223.   else
  1224.     regs[m_code->rd] = arm->cpsr.blk;
  1225.   return 1;
  1226. }
  1227.  
  1228. finline void
  1229. isa_arm7_store_psr_base (struct gba *const agb,
  1230.                                   const uint32_t r,
  1231.                                   const uint32_t c,
  1232.                                   const uint32_t f,   const uint32_t value)
  1233. {
  1234.   struct psr nw_psr;
  1235.   struct psr org_psr;
  1236.  
  1237.   nw_psr.blk = value;
  1238.   org_psr.blk = agb->arm7.cpsr.blk;
  1239.  
  1240.   if (r != 0) {
  1241.     /* write spsr */
  1242.     struct psr *const spsr = arm7_cur_spsr (agb);
  1243.     if (f != 0) {
  1244.       spsr->n = nw_psr.n;
  1245.       spsr->z = nw_psr.z;
  1246.       spsr->c = nw_psr.c;
  1247.       spsr->v = nw_psr.v;
  1248.     }
  1249.     if (c != 0) {
  1250.       spsr->mode = nw_psr.mode;
  1251.       spsr->irq = nw_psr.irq;
  1252.       spsr->fiq = nw_psr.fiq;
  1253.       spsr->thumb = nw_psr.thumb;
  1254.       spsr->mode |= 0x10;
  1255.     }
  1256.   } else {
  1257.     if (arm7_privilege_mode (agb) != false) {
  1258.       if (c == 0) {
  1259.         if (f != 0) {
  1260.           agb->arm7.cpsr.n = nw_psr.n;
  1261.           agb->arm7.cpsr.z = nw_psr.z;
  1262.           agb->arm7.cpsr.c = nw_psr.c;
  1263.           agb->arm7.cpsr.v = nw_psr.v;
  1264.         }
  1265.       } else {
  1266.         uint32_t nw_mode = nw_psr.mode & 0x0f;
  1267.         uint32_t org_mode = agb->arm7.cpsr.mode & 0x0f;
  1268.         if (org_mode != nw_mode) {
  1269.           /* will swtch mode */
  1270.           arm7_mode_switch (agb, nw_mode);
  1271.         }
  1272.        
  1273.         agb->arm7.cpsr.mode = nw_psr.mode | 0x10; /* or mode mask */
  1274.         agb->arm7.cpsr.irq = nw_psr.irq;
  1275.         agb->arm7.cpsr.fiq = nw_psr.fiq;
  1276.         agb->arm7.cpsr.thumb = 0;
  1277.  
  1278.         if (f != 0) {
  1279.           agb->arm7.cpsr.n = nw_psr.n;
  1280.           agb->arm7.cpsr.z = nw_psr.z;
  1281.           agb->arm7.cpsr.c = nw_psr.c;
  1282.           agb->arm7.cpsr.v = nw_psr.v;
  1283.         } else {
  1284.           agb->arm7.cpsr.n = org_psr.n;
  1285.           agb->arm7.cpsr.z = org_psr.z;
  1286.           agb->arm7.cpsr.c = org_psr.c;
  1287.           agb->arm7.cpsr.v = org_psr.v;
  1288.         }
  1289.       }
  1290.     } else {
  1291.       /* in user mode, only write field_f */
  1292.       if (f != 0) {
  1293.         agb->arm7.cpsr.n = nw_psr.n;
  1294.         agb->arm7.cpsr.z = nw_psr.z;
  1295.         agb->arm7.cpsr.c = nw_psr.c;
  1296.         agb->arm7.cpsr.v = nw_psr.v;
  1297.       }
  1298.     }
  1299.   }
  1300. }
  1301.  
  1302. finline
  1303. int32_t isa_arm7_psr_store_imm (struct gba *const agb,
  1304.                                   const uint32_t opcode)
  1305. {
  1306.   struct arm7 *const arm = & agb->arm7;
  1307.   uint32_t *const regs = & arm->regs[0];
  1308.   const struct arm_msr_rot_imm32 *const m_code = (const struct arm_msr_rot_imm32 *const) & opcode;
  1309.   const uint32_t imm32 = arm7_alu_helper_rot_imm32 (m_code->imm8, m_code->rotate_imm, null);
  1310.  
  1311.   isa_arm7_store_psr_base (agb, m_code->r, m_code->field_c, m_code->field_f, imm32);
  1312.   return 1;
  1313. }
  1314.  
  1315. finline
  1316. int32_t isa_arm7_psr_store_reg (struct gba *const agb,
  1317.                                   const uint32_t opcode)
  1318. {
  1319.   struct arm7 *const arm = & agb->arm7;
  1320.   uint32_t *const regs = & arm->regs[0];
  1321.   const struct arm_msr_reg *const m_code = (const struct arm_msr_reg *const) & opcode;
  1322.  
  1323.   isa_arm7_store_psr_base (agb, m_code->r, m_code->field_c, m_code->field_f, regs [m_code->rm]);
  1324.   return 1;
  1325. }
  1326.  
  1327. finline
  1328. int32_t isa_arm7_memory_access_ubw_base (struct gba *const agb,
  1329.                                   const uint32_t p,
  1330.                                   const uint32_t u,
  1331.                                   const uint32_t b,
  1332.                                   const uint32_t w,
  1333.                                   const uint32_t l,
  1334.                                   const uint32_t rn,
  1335.                                   const uint32_t rd,
  1336.                                   const uint32_t rhs)
  1337. {
  1338.   struct arm7 *const arm = & agb->arm7;
  1339.   uint32_t *const regs = & arm->regs[0];
  1340.   int32_t wait_state;
  1341.   uint32_t rn_writeback;
  1342.   uint32_t rn_address;
  1343.   uint32_t rn_init = regs[rn];
  1344.  
  1345.   if (u != 0)
  1346.     rn_writeback = regs[rn] + rhs;
  1347.   else
  1348.     rn_writeback = regs[rn] - rhs;
  1349.  
  1350.   if (p != 0)
  1351.     rn_address = rn_writeback;
  1352.   else
  1353.     rn_address = regs[rn];
  1354.  
  1355.   if (l != 0) {
  1356.     if (b != 0) {
  1357.       /* LDRB/LDRBT instruction */
  1358.       uint8_t memory;
  1359.      
  1360.       wait_state = agb_mbus_rb ( agb, rn_address, & memory, false) + 3;
  1361.       regs[rd] = memory;
  1362.     } else {
  1363.       /* LDR/LDRT instruction */
  1364.       uint32_t memory;
  1365.       const uint32_t rot_bit = (rn_address & 3) << 3;
  1366.  
  1367.       wait_state = agb_mbus_rw ( agb, rn_address, & memory, false) + 3;
  1368.       if (rot_bit == 0)
  1369.         regs[rd] = memory;
  1370.       else
  1371.         regs[rd] = memory >> rot_bit | memory << (32 - rot_bit);
  1372.       if (rd == 15) {
  1373.         /* flush pipeline */
  1374.         regs[rd] &= ARM7_CODE_MASK;
  1375.         return arm7_flush (agb) + 2 + wait_state;
  1376.       }
  1377.     }
  1378.     if (    (w != 0 || p == 0)
  1379.       && rd != rn)
  1380.       regs[rn] = rn_writeback;
  1381.   } else {
  1382.     if (b != 0) {
  1383.       /* STRB/STRBT instruction */
  1384.       wait_state = agb_mbus_wb ( agb, rn_address,  regs[rd], false) + 2;
  1385.     } else {
  1386.       /* STR/STRT instruction */
  1387.       wait_state = agb_mbus_ww ( agb, rn_address, rd == 15 ? regs[rd] + 4 : regs[rd], false) + 2;
  1388.     }
  1389.     if ( (w != 0 || p == 0))
  1390.       regs[rn] = rn_writeback;
  1391.   }
  1392.   return wait_state;
  1393. }
  1394.  
  1395. finline
  1396. int32_t isa_arm7_memory_access_ubw_imm12 (struct gba *const agb,
  1397.                                   const uint32_t opcode,
  1398.                                   const uint32_t p,
  1399.                                   const uint32_t u,
  1400.                                   const uint32_t b,
  1401.                                   const uint32_t w,
  1402.                                   const uint32_t l )
  1403. {
  1404.   struct arm7 *const arm = & agb->arm7;
  1405.   uint32_t *const regs = & arm->regs[0];
  1406.   const struct arm_memory_access_ubw_imm12 *const m_code = (const struct arm_memory_access_ubw_imm12 *const) & opcode;
  1407.   return isa_arm7_memory_access_ubw_base (agb, p, u, b, w, l, m_code->rn, m_code->rd, m_code->offset12);
  1408. }
  1409.  
  1410. finline
  1411. int32_t isa_arm7_memory_access_ubw_reg(struct gba *const agb,
  1412.                                   const uint32_t opcode,
  1413.                                   const uint32_t p,
  1414.                                   const uint32_t u,
  1415.                                   const uint32_t b,
  1416.                                   const uint32_t w,
  1417.                                   const uint32_t l )
  1418. {
  1419.   struct arm7 *const arm = & agb->arm7;
  1420.   uint32_t *const regs = & arm->regs[0];
  1421.   const struct arm_memory_access_sbh_reg *const m_code = (const struct arm_memory_access_sbh_reg *const) & opcode;
  1422.   return isa_arm7_memory_access_ubw_base (agb, p, u, b, w, l, m_code->rn, m_code->rd, regs[m_code->rm]);
  1423. }
  1424.  
  1425. finline
  1426. int32_t isa_arm7_memory_access_ubw_scaled(struct gba *const agb,
  1427.                                   const uint32_t opcode,
  1428.                                   const uint32_t shift,
  1429.                                   const uint32_t p,
  1430.                                   const uint32_t u,
  1431.                                   const uint32_t b,
  1432.                                   const uint32_t w,
  1433.                                   const uint32_t l )
  1434. {
  1435.   struct arm7 *const arm = & agb->arm7;
  1436.   uint32_t *const regs = & arm->regs[0];
  1437.   const struct arm_memory_access_ubw_scaled *const m_code = (const struct arm_memory_access_ubw_scaled *const) & opcode;
  1438.   const uint32_t scaled = arm7_alu_shift_imm5 (arm, regs[m_code->rm], shift, m_code->shift_imm, null);
  1439.   return isa_arm7_memory_access_ubw_base (agb, p, u, b, w, l, m_code->rn, m_code->rd, scaled);
  1440. }
  1441.  
  1442. finline
  1443. int32_t isa_arm7_list_memory_access_load (struct gba *const agb,
  1444.                                   const uint32_t opcode,
  1445.                                   const uint32_t p,
  1446.                                   const uint32_t u,
  1447.                                   const uint32_t s,
  1448.                                   const uint32_t w)
  1449. #undef LDM_VECTOR_ADD
  1450. #define LDM_VECTOR_ADD 0
  1451. #undef LDM_VECTOR_SUB
  1452. #define LDM_VECTOR_SUB 1
  1453. #undef LDM_ELEM
  1454.  
  1455. #define LDM_ELEM(n, vector)\
  1456.   do {                                                          \
  1457.      if (m_code->r##n != 0) { \
  1458.        wait_state += agb_mbus_rw (agb, rn_base, & regs[n], true) + 1;\
  1459.        if (vector == LDM_VECTOR_ADD)\
  1460.          rn_base += 4; \
  1461.        else if (vector == LDM_VECTOR_SUB)\
  1462.          rn_base -= 4;\
  1463.        else \
  1464.          assert (0);\
  1465.      }\
  1466.   } while (0)
  1467.  
  1468. #undef LDM_ELEM_R13_R14_BANK
  1469. #define LDM_ELEM_R13_R14_BANK(n, vector)\
  1470.   do {                                                          \
  1471.      if (m_code->r##n != 0) { \
  1472.        wait_state += agb_mbus_rw (agb, rn_base, & arm->r1314_t[R1314b_SYSUSER+((n) - 13)], true) + 1;\
  1473.        if (vector == LDM_VECTOR_ADD)\
  1474.          rn_base += 4; \
  1475.        else if (vector == LDM_VECTOR_SUB)\
  1476.          rn_base -= 4;\
  1477.        else \
  1478.          assert (0);\
  1479.      }\
  1480.   } while (0)
  1481.  
  1482. #undef LDM_ELEM_R8_R12_BANK
  1483. #define LDM_ELEM_R8_R12_BANK(n, vector)\
  1484.   do {                                                          \
  1485.      if (m_code->r##n != 0) { \
  1486.        wait_state += agb_mbus_rw (agb, rn_base, & arm->r812_t[R812b_EXCEPT_FIQ+((n) - 8)], true) + 1;\
  1487.        if (vector == LDM_VECTOR_ADD)\
  1488.          rn_base += 4; \
  1489.        else if (vector == LDM_VECTOR_SUB)\
  1490.          rn_base -= 4;\
  1491.        else \
  1492.          assert (0);\
  1493.      }\
  1494.   } while (0)
  1495.    
  1496. #define LDM_ALL_BASE_POST() \
  1497.   do {                    \
  1498.     LDM_ELEM (0, LDM_VECTOR_ADD); \
  1499.     LDM_ELEM (1, LDM_VECTOR_ADD); \
  1500.     LDM_ELEM (2, LDM_VECTOR_ADD); \
  1501.     LDM_ELEM (3, LDM_VECTOR_ADD); \
  1502.     LDM_ELEM (4, LDM_VECTOR_ADD); \
  1503.     LDM_ELEM (5, LDM_VECTOR_ADD); \
  1504.     LDM_ELEM (6, LDM_VECTOR_ADD); \
  1505.     LDM_ELEM (7, LDM_VECTOR_ADD); \
  1506.   }  while (0)
  1507.  
  1508. #define LDM_ALL_BASE_NEG() \
  1509.   do {                    \
  1510.     LDM_ELEM (7, LDM_VECTOR_SUB); \
  1511.     LDM_ELEM (6, LDM_VECTOR_SUB); \
  1512.     LDM_ELEM (5, LDM_VECTOR_SUB); \
  1513.     LDM_ELEM (4, LDM_VECTOR_SUB); \
  1514.     LDM_ELEM (3, LDM_VECTOR_SUB); \
  1515.     LDM_ELEM (2, LDM_VECTOR_SUB); \
  1516.     LDM_ELEM (1, LDM_VECTOR_SUB); \
  1517.     LDM_ELEM (0, LDM_VECTOR_SUB); \
  1518.   }  while (0)
  1519.    
  1520. #undef LDM_ALL_STD_POST
  1521. #define LDM_ALL_STD_POST() \
  1522.   do {                    \
  1523.     LDM_ALL_BASE_POST (); \
  1524.     LDM_ELEM (8, LDM_VECTOR_ADD); \
  1525.     LDM_ELEM (9, LDM_VECTOR_ADD); \
  1526.     LDM_ELEM (10, LDM_VECTOR_ADD); \
  1527.     LDM_ELEM (11, LDM_VECTOR_ADD); \
  1528.     LDM_ELEM (12, LDM_VECTOR_ADD); \
  1529.     LDM_ELEM (13, LDM_VECTOR_ADD); \
  1530.     LDM_ELEM (14, LDM_VECTOR_ADD); \
  1531.     LDM_ELEM (15, LDM_VECTOR_ADD);\
  1532.   }  while (0)
  1533.  
  1534. #undef LDM_ALL_STD_NEG
  1535. #define LDM_ALL_STD_NEG() \
  1536.   do {                    \
  1537.     LDM_ELEM (15, LDM_VECTOR_SUB); \
  1538.     LDM_ELEM (14, LDM_VECTOR_SUB); \
  1539.     LDM_ELEM (13, LDM_VECTOR_SUB); \
  1540.     LDM_ELEM (12, LDM_VECTOR_SUB); \
  1541.     LDM_ELEM (11, LDM_VECTOR_SUB); \
  1542.     LDM_ELEM (10, LDM_VECTOR_SUB); \
  1543.     LDM_ELEM (9, LDM_VECTOR_SUB); \
  1544.     LDM_ELEM (8, LDM_VECTOR_SUB);\
  1545.     LDM_ALL_BASE_NEG ();\
  1546.   }  while (0)                                
  1547. {
  1548.   struct arm7 *const arm = & agb->arm7;
  1549.   uint32_t *const regs = & arm->regs[0];
  1550.   const struct arm_list_memory_access *const m_code = (const struct arm_list_memory_access *const) & opcode;
  1551.   uint32_t rn_base = rn_base = regs[m_code->rn] & ARM7_MEM_MASK;
  1552.   uint32_t wait_state = 0;
  1553.   uint32_t list = opcode & 0xffff;
  1554.  
  1555.   if (p != 0)
  1556.     if (u != 0)
  1557.       rn_base = regs[m_code->rn] + 4 & ARM7_MEM_MASK;
  1558.     else
  1559.       rn_base = regs[m_code->rn] - 4 & ARM7_MEM_MASK;
  1560.   else ;
  1561.  
  1562.   if (s != 0) {
  1563.     if (m_code->r15 != 0) {
  1564.       /* current mode ldm, switch sys-mode */
  1565.       if (u != 0) {
  1566.         LDM_ALL_STD_POST ();
  1567.       } else {
  1568.         LDM_ALL_STD_NEG ();
  1569.       }
  1570.       spsr_to_cpsr (agb);
  1571.     } else {
  1572.       /* user-mode ldm */
  1573.       const uint32_t mode = arm->cpsr.mode & 0x0f;
  1574.      
  1575.       if (mode ==  0x0f
  1576.         || mode == 0x00)
  1577.       {  
  1578.         /* sys or user mode, use same register bank */
  1579.         if (u != 0)
  1580.         {
  1581.           LDM_ALL_STD_POST ();
  1582.         }
  1583.         else
  1584.         {
  1585.           LDM_ALL_STD_NEG ();
  1586.         }
  1587.       }
  1588.       else
  1589.       {
  1590.         if (mode == 0x01)
  1591.         {
  1592.           /* fiq mode */
  1593.           if (u != 0)
  1594.           {
  1595.             LDM_ALL_BASE_POST ();
  1596.             LDM_ELEM_R8_R12_BANK (8, LDM_VECTOR_ADD);
  1597.             LDM_ELEM_R8_R12_BANK (9, LDM_VECTOR_ADD);
  1598.             LDM_ELEM_R8_R12_BANK (10, LDM_VECTOR_ADD);
  1599.             LDM_ELEM_R8_R12_BANK (11, LDM_VECTOR_ADD);
  1600.             LDM_ELEM_R8_R12_BANK (12, LDM_VECTOR_ADD);
  1601.             LDM_ELEM_R13_R14_BANK (13, LDM_VECTOR_ADD);
  1602.             LDM_ELEM_R13_R14_BANK (14, LDM_VECTOR_ADD);
  1603.             LDM_ELEM (15, LDM_VECTOR_ADD);
  1604.           }
  1605.           else
  1606.           {
  1607.             LDM_ELEM (15, LDM_VECTOR_SUB);
  1608.             LDM_ELEM_R13_R14_BANK (14, LDM_VECTOR_SUB);
  1609.             LDM_ELEM_R13_R14_BANK (13, LDM_VECTOR_SUB);
  1610.             LDM_ELEM_R8_R12_BANK (12, LDM_VECTOR_SUB);
  1611.             LDM_ELEM_R8_R12_BANK (11, LDM_VECTOR_SUB);
  1612.             LDM_ELEM_R8_R12_BANK (10, LDM_VECTOR_SUB);
  1613.             LDM_ELEM_R8_R12_BANK (9, LDM_VECTOR_SUB);
  1614.             LDM_ELEM_R8_R12_BANK (8, LDM_VECTOR_SUB);
  1615.             LDM_ALL_BASE_NEG ();
  1616.           }
  1617.         }
  1618.         else
  1619.         {
  1620.           /* not fiq mode */
  1621.           if (u != 0)
  1622.           {
  1623.             LDM_ALL_BASE_POST ();
  1624.             LDM_ELEM (8, LDM_VECTOR_ADD);
  1625.             LDM_ELEM (9, LDM_VECTOR_ADD);
  1626.             LDM_ELEM (10, LDM_VECTOR_ADD);
  1627.             LDM_ELEM (11, LDM_VECTOR_ADD);
  1628.             LDM_ELEM (12, LDM_VECTOR_ADD);
  1629.             LDM_ELEM_R13_R14_BANK (13, LDM_VECTOR_ADD);
  1630.             LDM_ELEM_R13_R14_BANK (14, LDM_VECTOR_ADD);
  1631.             LDM_ELEM (15, LDM_VECTOR_ADD);
  1632.           }
  1633.           else
  1634.           {
  1635.             LDM_ELEM (15, LDM_VECTOR_SUB);
  1636.             LDM_ELEM_R13_R14_BANK (14, LDM_VECTOR_SUB);
  1637.             LDM_ELEM_R13_R14_BANK (13, LDM_VECTOR_SUB);
  1638.             LDM_ELEM (12, LDM_VECTOR_SUB);
  1639.             LDM_ELEM (11, LDM_VECTOR_SUB);
  1640.             LDM_ELEM (10, LDM_VECTOR_SUB);
  1641.             LDM_ELEM (9, LDM_VECTOR_SUB);
  1642.             LDM_ELEM (8, LDM_VECTOR_SUB);
  1643.             LDM_ALL_BASE_NEG ();
  1644.           }
  1645.         }
  1646.       }
  1647.     }
  1648.   } else {
  1649.     /* current mode ldm */
  1650.     if (u != 0)
  1651.     {
  1652.       LDM_ALL_STD_POST ();
  1653.     }
  1654.     else
  1655.     {
  1656.       LDM_ALL_STD_NEG ();
  1657.     }
  1658.   }
  1659.   if (w != 0
  1660.     && (list & 1 << m_code->rn) == 0)
  1661.     if (p != 0)
  1662.       regs[m_code->rn] = rn_base + (u == 0 ? 4 : -4);
  1663.     else
  1664.       regs[m_code->rn] = rn_base;
  1665.  
  1666.   regs[m_code->rn] &= ARM7_CODE_MASK;
  1667.  
  1668.   if (m_code->r15 != 0)
  1669.     if (arm->cpsr.thumb !=0)
  1670.       return thumb_flush (agb) + wait_state + 4;
  1671.     else
  1672.       return arm7_flush (agb) + wait_state + 4;
  1673.   else
  1674.     return wait_state + 2;
  1675. }
  1676.  
  1677. finline
  1678. int32_t isa_arm7_list_memory_access_store (struct gba *const agb,
  1679.                                   const uint32_t opcode,
  1680.                                   const uint32_t p,
  1681.                                   const uint32_t u,
  1682.                                   const uint32_t s,
  1683.                                   const uint32_t w)
  1684. #undef STM_VECTOR_ADD
  1685. #define STM_VECTOR_ADD 0
  1686. #undef STM_VECTOR_SUB
  1687. #define STM_VECTOR_SUB 1
  1688. #undef STM_ELEM
  1689.  
  1690. #define STM_ELEM(n, vector)\
  1691.   do {                                                          \
  1692.      if (m_code->r##n != 0) { \
  1693.        wait_state += agb_mbus_ww (agb, rn_base, regs[n], true) + 1;\
  1694.        if (vector == STM_VECTOR_ADD)\
  1695.          rn_base += 4; \
  1696.        else if (vector == STM_VECTOR_SUB)\
  1697.          rn_base -= 4;\
  1698.        else \
  1699.          assert (0);\
  1700.      }\
  1701.   } while (0)
  1702.  
  1703. #undef STM_ELEM_R13_R14_BANK
  1704. #define STM_ELEM_R13_R14_BANK(n, vector)\
  1705.   do {                                                          \
  1706.      if (m_code->r##n != 0) { \
  1707.        wait_state += agb_mbus_ww (agb, rn_base, arm->r1314_t[R1314b_SYSUSER+((n) - 13)], true) + 1;\
  1708.        if (vector == STM_VECTOR_ADD)\
  1709.          rn_base += 4; \
  1710.        else if (vector == STM_VECTOR_SUB)\
  1711.          rn_base -= 4;\
  1712.        else \
  1713.          assert (0);\
  1714.      }\
  1715.   } while (0)
  1716.  
  1717. #undef STM_ELEM_R8_R12_BANK
  1718. #define STM_ELEM_R8_R12_BANK(n, vector)\
  1719.   do {                                                          \
  1720.      if (m_code->r##n != 0) { \
  1721.        wait_state += agb_mbus_ww (agb, rn_base, arm->r812_t[R812b_EXCEPT_FIQ+((n) - 8)], true) + 1;\
  1722.        if (vector == STM_VECTOR_ADD)\
  1723.          rn_base += 4; \
  1724.        else if (vector == STM_VECTOR_SUB)\
  1725.          rn_base -= 4;\
  1726.        else \
  1727.          assert (0);\
  1728.      }\
  1729.   } while (0)
  1730.    
  1731. #define STM_ALL_BASE_POST() \
  1732.   do {                    \
  1733.     STM_ELEM (0, STM_VECTOR_ADD); \
  1734.     STM_ELEM (1, STM_VECTOR_ADD); \
  1735.     STM_ELEM (2, STM_VECTOR_ADD); \
  1736.     STM_ELEM (3, STM_VECTOR_ADD); \
  1737.     STM_ELEM (4, STM_VECTOR_ADD); \
  1738.     STM_ELEM (5, STM_VECTOR_ADD); \
  1739.     STM_ELEM (6, STM_VECTOR_ADD); \
  1740.     STM_ELEM (7, STM_VECTOR_ADD); \
  1741.   }  while (0)
  1742.  
  1743. #define STM_ALL_BASE_NEG() \
  1744.   do {                    \
  1745.     STM_ELEM (7, STM_VECTOR_SUB); \
  1746.     STM_ELEM (6, STM_VECTOR_SUB); \
  1747.     STM_ELEM (5, STM_VECTOR_SUB); \
  1748.     STM_ELEM (4, STM_VECTOR_SUB); \
  1749.     STM_ELEM (3, STM_VECTOR_SUB); \
  1750.     STM_ELEM (2, STM_VECTOR_SUB); \
  1751.     STM_ELEM (1, STM_VECTOR_SUB); \
  1752.     STM_ELEM (0, STM_VECTOR_SUB); \
  1753.   }  while (0)
  1754.    
  1755. #undef STM_ALL_STD_POST
  1756. #define STM_ALL_STD_POST() \
  1757.   do {                    \
  1758.     STM_ALL_BASE_POST (); \
  1759.     STM_ELEM (8, STM_VECTOR_ADD); \
  1760.     STM_ELEM (9, STM_VECTOR_ADD); \
  1761.     STM_ELEM (10, STM_VECTOR_ADD); \
  1762.     STM_ELEM (11, STM_VECTOR_ADD); \
  1763.     STM_ELEM (12, STM_VECTOR_ADD); \
  1764.     STM_ELEM (13, STM_VECTOR_ADD); \
  1765.     STM_ELEM (14, STM_VECTOR_ADD); \
  1766.     STM_ELEM (15, STM_VECTOR_ADD);\
  1767.   }  while (0)
  1768.  
  1769. #undef STM_ALL_STD_NEG
  1770. #define STM_ALL_STD_NEG() \
  1771.   do {                    \
  1772.     STM_ELEM (15, STM_VECTOR_SUB); \
  1773.     STM_ELEM (14, STM_VECTOR_SUB); \
  1774.     STM_ELEM (13, STM_VECTOR_SUB); \
  1775.     STM_ELEM (12, STM_VECTOR_SUB); \
  1776.     STM_ELEM (11, STM_VECTOR_SUB); \
  1777.     STM_ELEM (10, STM_VECTOR_SUB); \
  1778.     STM_ELEM (9, STM_VECTOR_SUB); \
  1779.     STM_ELEM (8, STM_VECTOR_SUB);\
  1780.     STM_ALL_BASE_NEG ();\
  1781.   }  while (0)                            
  1782.                                  
  1783. {
  1784.   struct arm7 *const arm = & agb->arm7;
  1785.   uint32_t *const regs = & arm->regs[0];
  1786.   const struct arm_list_memory_access *const m_code = (const struct arm_list_memory_access *const) & opcode;
  1787.   uint32_t rn_base = regs[m_code->rn] & ARM7_MEM_MASK;
  1788.   uint32_t wait_state = 0;
  1789.   uint32_t list = opcode & 0xffff;
  1790.  
  1791.   if (p != 0)
  1792.     if (u != 0)
  1793.       rn_base = regs[m_code->rn] + 4 & ARM7_MEM_MASK;
  1794.     else
  1795.       rn_base = regs[m_code->rn] - 4 & ARM7_MEM_MASK;
  1796.   else ;
  1797.  
  1798.   if (s != 0) {
  1799.     /* user-mode stm */
  1800.     const uint32_t mode = arm->cpsr.mode & 0x0f;
  1801.    
  1802.     if (mode ==  0x0f
  1803.       || mode == 0x00)
  1804.     {  
  1805.       /* sys or user mode, use same register bank */
  1806.       if (u != 0)
  1807.       {
  1808.         STM_ALL_STD_POST ();
  1809.       }
  1810.       else
  1811.       {
  1812.         STM_ALL_STD_NEG ();
  1813.       }
  1814.     }
  1815.     else
  1816.     {
  1817.       if (mode == 0x01)
  1818.       {
  1819.         /* fiq mode */
  1820.         if (u != 0)
  1821.         {
  1822.           STM_ALL_BASE_POST ();
  1823.           STM_ELEM_R8_R12_BANK (8, STM_VECTOR_ADD);
  1824.           STM_ELEM_R8_R12_BANK (9, STM_VECTOR_ADD);
  1825.           STM_ELEM_R8_R12_BANK (10, STM_VECTOR_ADD);
  1826.           STM_ELEM_R8_R12_BANK (11, STM_VECTOR_ADD);
  1827.           STM_ELEM_R8_R12_BANK (12, STM_VECTOR_ADD);
  1828.           STM_ELEM_R13_R14_BANK (13, STM_VECTOR_ADD);
  1829.           STM_ELEM_R13_R14_BANK (14, STM_VECTOR_ADD);
  1830.           STM_ELEM (15, STM_VECTOR_ADD);
  1831.         }
  1832.         else
  1833.         {
  1834.           STM_ELEM (15, STM_VECTOR_SUB);
  1835.           STM_ELEM_R13_R14_BANK (14, STM_VECTOR_SUB);
  1836.           STM_ELEM_R13_R14_BANK (13, STM_VECTOR_SUB);
  1837.           STM_ELEM_R8_R12_BANK (12, STM_VECTOR_SUB);
  1838.           STM_ELEM_R8_R12_BANK (11, STM_VECTOR_SUB);
  1839.           STM_ELEM_R8_R12_BANK (10, STM_VECTOR_SUB);
  1840.           STM_ELEM_R8_R12_BANK (9, STM_VECTOR_SUB);
  1841.           STM_ELEM_R8_R12_BANK (8, STM_VECTOR_SUB);
  1842.           STM_ALL_BASE_NEG ();
  1843.         }
  1844.       }
  1845.       else
  1846.       {
  1847.         /* not fiq mode */
  1848.         if (u != 0)
  1849.         {
  1850.           STM_ALL_BASE_POST ();
  1851.           STM_ELEM (8, STM_VECTOR_ADD);
  1852.           STM_ELEM (9, STM_VECTOR_ADD);
  1853.           STM_ELEM (10, STM_VECTOR_ADD);
  1854.           STM_ELEM (11, STM_VECTOR_ADD);
  1855.           STM_ELEM (12, STM_VECTOR_ADD);
  1856.           STM_ELEM_R13_R14_BANK (13, STM_VECTOR_ADD);
  1857.           STM_ELEM_R13_R14_BANK (14, STM_VECTOR_ADD);
  1858.           STM_ELEM (15, STM_VECTOR_ADD);
  1859.         }
  1860.         else
  1861.         {
  1862.           STM_ELEM (15, STM_VECTOR_SUB);
  1863.           STM_ELEM_R13_R14_BANK (14, STM_VECTOR_SUB);
  1864.           STM_ELEM_R13_R14_BANK (13, STM_VECTOR_SUB);
  1865.           STM_ELEM (12, STM_VECTOR_SUB);
  1866.           STM_ELEM (11, STM_VECTOR_SUB);
  1867.           STM_ELEM (10, STM_VECTOR_SUB);
  1868.           STM_ELEM (9, STM_VECTOR_SUB);
  1869.           STM_ELEM (8, STM_VECTOR_SUB);
  1870.           STM_ALL_BASE_NEG ();
  1871.         }
  1872.       }
  1873.     }
  1874.   } else {
  1875.     /* current mode ldm */
  1876.     if (u != 0)
  1877.     {
  1878.       STM_ALL_STD_POST ();
  1879.     }
  1880.     else
  1881.     {
  1882.       STM_ALL_STD_NEG ();
  1883.     }
  1884.   }
  1885.   if (w != 0)
  1886.     if (p != 0)
  1887.       regs[m_code->rn] = rn_base + (u == 0 ? 4 : -4);
  1888.     else
  1889.       regs[m_code->rn] = rn_base;
  1890.   else ;
  1891.  
  1892.   regs[m_code->rn] &= ARM7_CODE_MASK;
  1893.   return wait_state + 1;
  1894. }
  1895.  
  1896. finline
  1897. int32_t isa_arm7_branch_with_link (struct gba *const agb,
  1898.                                   const uint32_t opcode)
  1899. {
  1900.   /* 27 26 25 24        23 22 21 20  19 - 16    15 - 12    11 10 9 8   7 6 5 4   3 2 1 0
  1901.       1  0  1  L                             Offset (d23-d0)                               B/BL */
  1902.   struct arm7 *const arm = & agb->arm7;
  1903.   uint32_t *const regs = & arm->regs[0];
  1904.   const struct arm_branch *const m_code = (const struct arm_branch *const) & opcode;
  1905.   const uint32_t pipeline_pc = (regs[15] & ARM7_CODE_MASK);
  1906.   const uint32_t link_reg = pipeline_pc - 4;
  1907.   uint32_t offset;
  1908.  
  1909.   if (m_code->sign_bit != 0) {
  1910.     const uint32_t _mask_0_22 = 0x7FFFFF;
  1911.     offset = (m_code->sign_imm & _mask_0_22 |  ~_mask_0_22) << 2;
  1912.   } else {
  1913.     offset = m_code->sign_imm << 2;
  1914.   }
  1915.   regs[14] = link_reg;
  1916.   regs[15] = pipeline_pc + offset;
  1917.  
  1918.   return arm7_flush (agb) + 3;
  1919. }
  1920.  
  1921. finline
  1922. int32_t isa_arm7_branch_without_link (struct gba *const agb,
  1923.                                   const uint32_t opcode)
  1924. {
  1925.   /* 27 26 25 24        23 22 21 20  19 - 16    15 - 12    11 10 9 8   7 6 5 4   3 2 1 0
  1926.       1  0  1  L                             Offset (d23-d0)                               B/BL */
  1927.   struct arm7 *const arm = & agb->arm7;
  1928.   uint32_t *const regs = & arm->regs[0];
  1929.   const struct arm_branch *const m_code = (const struct arm_branch *const) & opcode;
  1930.   const uint32_t pipeline_pc = (regs[15] & ARM7_CODE_MASK);
  1931.   uint32_t offset;
  1932.  
  1933.   if (m_code->sign_bit != 0) {
  1934.     const uint32_t _mask_0_22 = 0x7FFFFF;
  1935.     offset = (m_code->sign_imm & _mask_0_22 |  ~_mask_0_22) << 2;
  1936.   } else {
  1937.     offset = m_code->sign_imm << 2;
  1938.   }
  1939.   regs[15] = pipeline_pc + offset;
  1940.   return arm7_flush (agb) + 3;
  1941. }
  1942.  
  1943. finline
  1944. int32_t isa_arm7_swi (struct gba *const agb,
  1945.                                   const uint32_t opcode)
  1946. {
  1947.   /* 27 26 25 24        23 22 21 20  19 - 16    15 - 12    11 10 9 8   7 6 5 4   3 2 1 0
  1948.       1  1  1  1                    SWI Number (d23-d0)                              SWI */
  1949.   struct arm7 *const arm = & agb->arm7;
  1950.   uint32_t *const regs = & arm->regs[0];
  1951.   const struct arm_swi *const m_code = (const struct arm_swi *const) & opcode;
  1952.   const uint32_t pipeline_pc = regs[15] &  ARM7_CODE_MASK;
  1953.  
  1954.   arm7_mode_switch (agb, ARM7_MODE_MGR);
  1955.  
  1956.   arm->r1314_t[1+R1314b_MGR] = pipeline_pc  - 4;
  1957.   arm->spsr_t[SPSRb_MGR].blk =  arm->cpsr.blk;
  1958.   arm->regs[14] = pipeline_pc  - 4;
  1959.   arm->cpsr.mode = ARM7_MODE_MGR;
  1960.   arm->cpsr.thumb = 0;
  1961.   arm->cpsr.irq = 1;
  1962.   arm->regs[15] = 8;
  1963.  
  1964.   return arm7_flush (agb) + 3;
  1965. }
  1966.  
  1967. finline
  1968. int32_t isa_thumb_swi (struct gba *const agb,
  1969.                                   const uint32_t opcode)
  1970. {
  1971.   /* 27 26 25 24        23 22 21 20  19 - 16    15 - 12    11 10 9 8   7 6 5 4   3 2 1 0
  1972.       1  1  1  1                    SWI Number (d23-d0)                              SWI */
  1973.   struct arm7 *const arm = & agb->arm7;
  1974.   uint32_t *const regs = & arm->regs[0];
  1975.   const struct arm_swi *const m_code = (const struct arm_swi *const) & opcode;
  1976.   const uint32_t pipeline_pc = regs[15] &  THUMB_CODE_MASK;
  1977.   int32_t wait_state;
  1978.  
  1979.   arm7_mode_switch (agb, ARM7_MODE_MGR);
  1980.  
  1981.   arm->r1314_t[1+R1314b_MGR] = pipeline_pc  - 2;
  1982.   arm->spsr_t[SPSRb_MGR].blk =  arm->cpsr.blk;
  1983.  
  1984.   arm->cpsr.mode = ARM7_MODE_MGR;
  1985.   arm->cpsr.thumb = 0;
  1986.   arm->cpsr.irq = 1;
  1987.   arm->regs[15] = 8;
  1988.  
  1989.   arm->regs[14] = pipeline_pc  - 2;
  1990.  
  1991.   wait_state = arm7_flush (agb) + 3;
  1992.   arm->regs[15] = 14;
  1993.  
  1994.   return wait_state;
  1995. }
  1996.  
  1997. finline  int32_t
  1998. isa_thumb_alu (struct gba *const agb,
  1999.                                   const uint32_t rm_rs, /* index */
  2000.                                   const uint32_t rd_rn,/* index */
  2001.                                   const kable  update_rd,
  2002.                                   uint32_t (*const alu_operate) (const uint32_t rn, const uint32_t oprand2, const uint32_t carry, uint32_t *const output_ext),
  2003.                                   void (*const update_flags) (struct arm7 *const arm,
  2004.                                       const uint32_t shift_c,
  2005.                                       const uint32_t output,
  2006.                                       const uint32_t output_ext,
  2007.                                       const uint32_t sop_lhs,
  2008.                                       const uint32_t sop_rhs))
  2009. {
  2010.   struct arm7 *const arm = & agb->arm7;
  2011.   uint32_t *const regs = & arm->regs[0];
  2012.   uint32_t output_ext;
  2013.   uint32_t shift_c = arm->cpsr.c;
  2014.   const uint32_t rhs = regs[rm_rs];
  2015.   const uint32_t lhs = regs[rd_rn];
  2016.   const uint32_t output = alu_operate (lhs, rhs, arm->cpsr.c, & output_ext);
  2017.  
  2018.   if (update_rd != false) {
  2019.     regs[rd_rn] = output;
  2020.   }
  2021.   update_flags (arm, shift_c, output, output_ext, lhs, rhs);
  2022.   return 1;
  2023. }
  2024.  
  2025. finline
  2026. int32_t isa_thumb_ldr_pc (struct gba *const agb,
  2027.                                   const uint32_t rd, /* index */
  2028.                                   const uint32_t imm8)
  2029. {
  2030.   struct arm7 *const arm = & agb->arm7;
  2031.   uint32_t *const regs = & arm->regs[0];
  2032.   uint32_t const pc = regs[15] & ARM7_CODE_MASK;
  2033.   uint32_t const address = pc + imm8 * 4;
  2034.   return agb_mbus_rw ( agb, address, & regs[rd], false) + 3;
  2035. }
  2036.  
  2037. finline  int32_t
  2038. isa_thumb_add (struct gba *const agb,
  2039.                                   const uint32_t rhs,
  2040.                                   const uint32_t rn_value,
  2041.                                   const uint32_t rd/* index */)
  2042. {
  2043.   struct arm7 *const arm = & agb->arm7;
  2044.   uint32_t *const regs = & arm->regs[0];
  2045.   uint32_t output_ext;
  2046.   const uint32_t lhs = rn_value;
  2047.   const uint32_t output = alu_add (lhs, rhs, arm->cpsr.c, & output_ext);
  2048.  
  2049.   regs[rd] = output;
  2050.   update_flags_add (arm, 0, output, output_ext, lhs, rhs);
  2051.   return 1;
  2052. }
  2053.  
  2054. finline  int32_t
  2055. isa_thumb_sub (struct gba *const agb,
  2056.                                   const uint32_t rhs,
  2057.                                   const uint32_t rn_value,
  2058.                                   const uint32_t rd/* index */)
  2059. {
  2060.   struct arm7 *const arm = & agb->arm7;
  2061.   uint32_t *const regs = & arm->regs[0];
  2062.   uint32_t output_ext;
  2063.   const uint32_t lhs = rn_value;
  2064.   const uint32_t output = alu_sub (lhs, rhs, arm->cpsr.c, & output_ext);
  2065.  
  2066.   regs[rd] = output;
  2067.   update_flags_sub  (arm, 0, output, output_ext, lhs, rhs);
  2068.   return 1;
  2069. }
  2070.  
  2071. finline  int32_t
  2072. isa_thumb_neg (struct gba *const agb,
  2073.                                   const uint32_t rhs,
  2074.                                   const uint32_t rd/* index */)
  2075. {
  2076.   struct arm7 *const arm = & agb->arm7;
  2077.   uint32_t *const regs = & arm->regs[0];
  2078.   uint32_t output_ext;
  2079.   const uint32_t output = alu_sub (0, rhs, arm->cpsr.c, & output_ext);
  2080.  
  2081.   regs[rd] = output;
  2082.   update_flags_sub  (arm, 0, output, output_ext, 0, rhs);
  2083.   return 1;
  2084. }
  2085.  
  2086. finline  int32_t
  2087. isa_thumb_cmp (struct gba *const agb,
  2088.                                   const uint32_t rhs,
  2089.                                   const uint32_t rn_value)
  2090. {
  2091.   struct arm7 *const arm = & agb->arm7;
  2092.   uint32_t *const regs = & arm->regs[0];
  2093.   uint32_t output_ext;
  2094.   const uint32_t lhs = rn_value;
  2095.   const uint32_t output = alu_sub (lhs, rhs, arm->cpsr.c, & output_ext);
  2096.  
  2097.   update_flags_sub  (arm, 0, output, output_ext, lhs, rhs);
  2098.   return 1;
  2099. }
  2100.  
  2101. uint32_t old_r10 = 0;
  2102. uint32_t old_r1 = 0;
  2103. uint32_t old_pc = 0;
  2104. kable show_pc = false;
  2105.  
  2106. #include <Windows.h>
  2107.  
  2108. finline
  2109. uint32_t cpu_tick (struct gba *agb) {
  2110.  
  2111.   int consume = 0;
  2112.  
  2113.   struct arm7 *const arm = & agb->arm7;
  2114.   uint32_t *const regs = & arm->regs[0];
  2115.  
  2116.  
  2117.   //if (GetKeyState ('q') == 0x8000)
  2118.   //  show_pc = ! show_pc;
  2119.  
  2120.   //if (show_pc != false)
  2121.   //  printf ("oldpc %07x\n", old_pc);
  2122.  // if (old_pc == 0xA0)
  2123.    // __asm int 3
  2124.  
  2125.   do {
  2126.     /* check cpu mode */
  2127.     if (arm->cpsr.thumb != 0) {
  2128.      
  2129.       const uint16_t OP_code = arm->opcode[0];
  2130.       const uint32_t OP_throat = OP_code >> 6;
  2131.       const uint32_t OP_cond = OP_code & LSHIFT_RANGE_MASK (0x0F, 28);
  2132.       const uint32_t pc = regs[15] - 4;
  2133.       arm->opcode[0] = arm->opcode[1];
  2134.       consume +=  thumb_fecth_n (agb, regs[15], (uint16_t *const)& arm->opcode[1]);
  2135.       old_pc  = pc;
  2136.  
  2137. // /    if (pc == 0x126)
  2138.      //   __asm int 3
  2139.  
  2140.       switch (OP_throat) {
  2141.       case 0x100:
  2142.         {
  2143.           /* and rd, rm */
  2144.           const struct thumb_alu *const e5 = (const struct thumb_alu *const) & OP_code;
  2145.           const uint32_t output = regs[e5->rd_rn] & regs[e5->rm_rs];
  2146.           regs[e5->rd_rn] = output;
  2147.           update_flags_logic_fast (arm, output);
  2148.           consume ++;
  2149.         }
  2150.         break;
  2151.       case 0x101:
  2152.         {
  2153.           /* eor rd, rm */
  2154.           const struct thumb_alu *const e5 = (const struct thumb_alu *const) & OP_code;
  2155.           const uint32_t output = regs[e5->rd_rn] ^ regs[e5->rm_rs];
  2156.           regs[e5->rd_rn] = output;
  2157.           update_flags_logic_fast (arm, output);
  2158.           consume ++;
  2159.         }
  2160.         break;
  2161.       case 0x102:
  2162.         {
  2163.           /* lsl rd, rs */
  2164.           const struct thumb_alu *const e5 = (const struct thumb_alu *const) & OP_code;
  2165.            uint32_t carry = arm->cpsr.c;
  2166.           const uint32_t output = arm7_alu_shift_rs (arm, regs[e5->rd_rn], 0, regs[e5->rm_rs], & carry);
  2167.  
  2168.           regs[e5->rd_rn] = output;
  2169.           update_flags_logic_fast (arm, output);
  2170.           arm->cpsr.c = carry;
  2171.           consume += 2;
  2172.         }
  2173.         break;
  2174.       case 0x103:
  2175.         {
  2176.           /* lsr rd, rs */
  2177.           const struct thumb_alu *const e5 = (const struct thumb_alu *const) & OP_code;
  2178.            uint32_t carry = arm->cpsr.c;
  2179.           const uint32_t output = arm7_alu_shift_rs (arm, regs[e5->rd_rn], 1, regs[e5->rm_rs], & carry);
  2180.  
  2181.           regs[e5->rd_rn] = output;
  2182.           update_flags_logic_fast (arm, output);
  2183.           arm->cpsr.c = carry;
  2184.           consume += 2;
  2185.         }
  2186.         break;
  2187.       case 0x104:
  2188.         {
  2189.           /* asr rd, rs */
  2190.           const struct thumb_alu *const e5 = (const struct thumb_alu *const) & OP_code;
  2191.            uint32_t carry = arm->cpsr.c;
  2192.           const uint32_t output = arm7_alu_shift_rs (arm, regs[e5->rd_rn], 2, regs[e5->rm_rs], & carry);
  2193.  
  2194.           regs[e5->rd_rn] = output;
  2195.           update_flags_logic_fast (arm, output);
  2196.           arm->cpsr.c = carry;
  2197.           consume += 2;
  2198.         }
  2199.         break;
  2200.       case 0x105:
  2201.         {
  2202.           /* adc rd, rm */
  2203.           const struct thumb_alu *const e5 = (const struct thumb_alu *const) & OP_code;
  2204.           consume += isa_thumb_alu (agb, e5->rm_rs, e5->rd_rn, true, alu_adc, update_flags_add);
  2205.         }
  2206.         break;
  2207.       case 0x106:
  2208.         {
  2209.           /* sbc rd, rm */
  2210.           const struct thumb_alu *const e5 = (const struct thumb_alu *const) & OP_code;
  2211.           consume += isa_thumb_alu (agb, e5->rm_rs, e5->rd_rn, true, alu_sbc, update_flags_sub);
  2212.         }
  2213.         break;
  2214.       case 0x107:
  2215.         {
  2216.           /* ror rd, rs */
  2217.           const struct thumb_alu *const e5 = (const struct thumb_alu *const) & OP_code;
  2218.            uint32_t carry = arm->cpsr.c;
  2219.           const uint32_t output = arm7_alu_shift_rs (arm, regs[e5->rd_rn], 3, regs[e5->rm_rs], & carry);
  2220.  
  2221.           regs[e5->rd_rn] = output;
  2222.           update_flags_logic_fast (arm, output);
  2223.           arm->cpsr.c = carry;
  2224.           consume += 2;
  2225.         }
  2226.         break;
  2227.       case 0x108:
  2228.         {
  2229.           /* tst rn, rm */
  2230.           const struct thumb_alu *const e5 = (const struct thumb_alu *const) & OP_code;
  2231.           consume += isa_thumb_alu (agb, e5->rm_rs, e5->rd_rn, false, alu_and, update_flags_logic);
  2232.         }
  2233.         break;
  2234.       case 0x109:
  2235.         {
  2236.           /* neg rd, rm */
  2237.           const struct thumb_alu *const e5 = (const struct thumb_alu *const) & OP_code;
  2238.           consume += isa_thumb_neg (agb, regs[e5->rm_rs], e5->rd_rn);
  2239.         }
  2240.         break;
  2241.       case 0x10A:
  2242.         {
  2243.           /* cmp rn, rm */
  2244.           const struct thumb_alu *const e5 = (const struct thumb_alu *const) & OP_code;
  2245.           consume += isa_thumb_alu (agb, e5->rm_rs, e5->rd_rn, false, alu_sub, update_flags_sub);
  2246.         }
  2247.         break;
  2248.       case 0x10B:
  2249.         {
  2250.           /* cmn rd, rm */
  2251.           const struct thumb_alu *const e5 = (const struct thumb_alu *const) & OP_code;
  2252.           consume += isa_thumb_alu (agb, e5->rm_rs, e5->rd_rn, false, alu_add, update_flags_add);
  2253.         }
  2254.         break;
  2255.       case 0x10C:
  2256.         {
  2257.           /* orr rd, rm */
  2258.           const struct thumb_alu *const e5 = (const struct thumb_alu *const) & OP_code;
  2259.           consume += isa_thumb_alu (agb, e5->rm_rs, e5->rd_rn, true, alu_orr, update_flags_logic);
  2260.         }
  2261.         break;
  2262.       case 0x10D:
  2263.         {
  2264.           /* mul rd, rs */
  2265.           const struct thumb_alu *const e5 = (const struct thumb_alu *const) & OP_code;
  2266.           const uint32_t rs_value =  regs[e5->rm_rs];
  2267.           const uint32_t output = regs[e5->rd_rn] * rs_value;
  2268.  
  2269.           regs[e5->rd_rn] = output;
  2270.           arm->cpsr.c = 0; /* Destroy flag-c */
  2271.          
  2272.           update_flags_logic_fast (arm, output);
  2273.           consume += mul_clks (rs_value) + 1 + 1;
  2274.         }
  2275.         break;
  2276.       case 0x10E:
  2277.         {
  2278.           /* bic rd, rm */
  2279.           const struct thumb_alu *const e5 = (const struct thumb_alu *const) & OP_code;
  2280.           consume += isa_thumb_alu (agb, e5->rm_rs, e5->rd_rn, true, alu_bic, update_flags_logic);
  2281.         }
  2282.         break;
  2283.       case 0x10F:
  2284.         {
  2285.           /* mvn rd, rm */
  2286.           const struct thumb_alu *const e5 = (const struct thumb_alu *const) & OP_code;
  2287.           consume += isa_thumb_alu (agb, e5->rm_rs, e5->rd_rn, true, alu_mvn, update_flags_logic);
  2288.         }
  2289.         break;
  2290.       case 0x1C << 5 | 0:
  2291.       case 0x1C << 5 | 1:
  2292.       case 0x1C << 5 | 2:
  2293.       case 0x1C << 5 | 3:
  2294.       case 0x1C << 5 | 4:
  2295.       case 0x1C << 5 | 5:
  2296.       case 0x1C << 5 | 6:
  2297.       case 0x1C << 5 | 7:
  2298.       case 0x1C << 5 | 8:
  2299.       case 0x1C << 5 | 9:
  2300.       case 0x1C << 5 |10:
  2301.       case 0x1C << 5 |11:
  2302.       case 0x1C << 5 |12:
  2303.       case 0x1C << 5 |13:
  2304.       case 0x1C << 5 |14:
  2305.       case 0x1C << 5 |15:
  2306.       case 0x1C << 5 |16:
  2307.       case 0x1C << 5 |17:
  2308.       case 0x1C << 5 |18:
  2309.       case 0x1C << 5 |19:
  2310.       case 0x1C << 5 |20:
  2311.       case 0x1C << 5 |21:
  2312.       case 0x1C << 5 |22:
  2313.       case 0x1C << 5 |23:
  2314.       case 0x1C << 5 |24:
  2315.       case 0x1C << 5 |25:
  2316.       case 0x1C << 5 |26:
  2317.       case 0x1C << 5 |27:
  2318.       case 0x1C << 5 |28:
  2319.       case 0x1C << 5 |29:
  2320.       case 0x1C << 5 |30:
  2321.       case 0x1C << 5 |31:
  2322.         {
  2323.           const struct thumb_branch *const m_code = (const struct thumb_branch *const) & OP_code;
  2324.           const uint32_t pipeline_pc = regs[15];
  2325.           uint32_t offset;
  2326.  
  2327.           if (m_code->sign_bit != 0) {
  2328.             const uint32_t _mask_0_9 = 0x3FF;
  2329.             offset = ((uint32_t) m_code->imm10 & (uint32_t) _mask_0_9 |  ~ (uint32_t)_mask_0_9) << 1 ;
  2330.           } else {
  2331.             offset = (uint32_t) m_code->imm10 << 1;
  2332.           }
  2333.           regs[15] = pipeline_pc + offset;
  2334.           consume += thumb_flush (agb) + 3;
  2335.         }
  2336.         break;
  2337.  
  2338.       case 0x1E << 5 | 0:
  2339.       case 0x1E << 5 | 1:
  2340.       case 0x1E << 5 | 2:
  2341.       case 0x1E << 5 | 3:
  2342.       case 0x1E << 5 | 4:
  2343.       case 0x1E << 5 | 5:
  2344.       case 0x1E << 5 | 6:
  2345.       case 0x1E << 5 | 7:
  2346.       case 0x1E << 5 | 8:
  2347.       case 0x1E << 5 | 9:
  2348.       case 0x1E << 5 |10:
  2349.       case 0x1E << 5 |11:
  2350.       case 0x1E << 5 |12:
  2351.       case 0x1E << 5 |13:
  2352.       case 0x1E << 5 |14:
  2353.       case 0x1E << 5 |15:
  2354.       case 0x1E << 5 |16:
  2355.       case 0x1E << 5 |17:
  2356.       case 0x1E << 5 |18:
  2357.       case 0x1E << 5 |19:
  2358.       case 0x1E << 5 |20:
  2359.       case 0x1E << 5 |21:
  2360.       case 0x1E << 5 |22:
  2361.       case 0x1E << 5 |23:
  2362.       case 0x1E << 5 |24:
  2363.       case 0x1E << 5 |25:
  2364.       case 0x1E << 5 |26:
  2365.       case 0x1E << 5 |27:
  2366.       case 0x1E << 5 |28:
  2367.       case 0x1E << 5 |29:
  2368.       case 0x1E << 5 |30:
  2369.       case 0x1E << 5 |31:
  2370.         {
  2371.           const struct thumb_branch *const m_code = (const struct thumb_branch *const) & OP_code;
  2372.           const uint32_t pipeline_pc = regs[15];
  2373.           uint32_t offset;
  2374.  
  2375.           if (m_code->sign_bit != 0) {
  2376.             const uint32_t _mask_0_9 = 0x3FF;
  2377.             offset = (uint32_t) m_code->imm10 & _mask_0_9 |  ~_mask_0_9;
  2378.           } else {
  2379.             offset = (uint32_t) m_code->imm10;
  2380.           }
  2381.           regs[14] = pipeline_pc + (offset << 12);
  2382.           consume += 1;
  2383.         }
  2384.         break;
  2385.  
  2386.       case 0x1F << 5 | 0:
  2387.       case 0x1F << 5 | 1:
  2388.       case 0x1F << 5 | 2:
  2389.       case 0x1F << 5 | 3:
  2390.       case 0x1F << 5 | 4:
  2391.       case 0x1F << 5 | 5:
  2392.       case 0x1F << 5 | 6:
  2393.       case 0x1F << 5 | 7:
  2394.       case 0x1F << 5 | 8:
  2395.       case 0x1F << 5 | 9:
  2396.       case 0x1F << 5 |10:
  2397.       case 0x1F << 5 |11:
  2398.       case 0x1F << 5 |12:
  2399.       case 0x1F << 5 |13:
  2400.       case 0x1F << 5 |14:
  2401.       case 0x1F << 5 |15:
  2402.       case 0x1F << 5 |16:
  2403.       case 0x1F << 5 |17:
  2404.       case 0x1F << 5 |18:
  2405.       case 0x1F << 5 |19:
  2406.       case 0x1F << 5 |20:
  2407.       case 0x1F << 5 |21:
  2408.       case 0x1F << 5 |22:
  2409.       case 0x1F << 5 |23:
  2410.       case 0x1F << 5 |24:
  2411.       case 0x1F << 5 |25:
  2412.       case 0x1F << 5 |26:
  2413.       case 0x1F << 5 |27:
  2414.       case 0x1F << 5 |28:
  2415.       case 0x1F << 5 |29:
  2416.       case 0x1F << 5 |30:
  2417.       case 0x1F << 5 |31:
  2418.         {
  2419.           const uint32_t save_lrlink = (regs[15] &  THUMB_CODE_MASK) - 2 | 1;
  2420.           regs[15] = regs[14] + (OP_code & 0x7FF) * 2;
  2421.           regs[14] = save_lrlink;
  2422.  
  2423.           consume += thumb_flush (agb) + 3;;
  2424.         }
  2425.         break;
  2426.       case 0x18 << 5 | 0:
  2427.       case 0x18 << 5 | 1:
  2428.       case 0x18 << 5 | 2:
  2429.       case 0x18 << 5 | 3:
  2430.       case 0x18 << 5 | 4:
  2431.       case 0x18 << 5 | 5:
  2432.       case 0x18 << 5 | 6:
  2433.       case 0x18 << 5 | 7:
  2434.       case 0x18 << 5 | 8:
  2435.       case 0x18 << 5 | 9:
  2436.       case 0x18 << 5 |10:
  2437.       case 0x18 << 5 |11:
  2438.       case 0x18 << 5 |12:
  2439.       case 0x18 << 5 |13:
  2440.       case 0x18 << 5 |14:
  2441.       case 0x18 << 5 |15:
  2442.       case 0x18 << 5 |16:
  2443.       case 0x18 << 5 |17:
  2444.       case 0x18 << 5 |18:
  2445.       case 0x18 << 5 |19:
  2446.       case 0x18 << 5 |20:
  2447.       case 0x18 << 5 |21:
  2448.       case 0x18 << 5 |22:
  2449.       case 0x18 << 5 |23:
  2450.       case 0x18 << 5 |24:
  2451.       case 0x18 << 5 |25:
  2452.       case 0x18 << 5 |26:
  2453.       case 0x18 << 5 |27:
  2454.       case 0x18 << 5 |28:
  2455.       case 0x18 << 5 |29:
  2456.       case 0x18 << 5 |30:
  2457.       case 0x18 << 5 |31:
  2458.          consume +=  isa_arm7_list_memory_access_store (agb, OP_code & 0xFF | (OP_code >>8 & 7) << 16, 0, 1, 0, 1);
  2459.          break;
  2460.       case 0x19 << 5 | 0:
  2461.       case 0x19 << 5 | 1:
  2462.       case 0x19 << 5 | 2:
  2463.       case 0x19 << 5 | 3:
  2464.       case 0x19 << 5 | 4:
  2465.       case 0x19 << 5 | 5:
  2466.       case 0x19 << 5 | 6:
  2467.       case 0x19 << 5 | 7:
  2468.       case 0x19 << 5 | 8:
  2469.       case 0x19 << 5 | 9:
  2470.       case 0x19 << 5 |10:
  2471.       case 0x19 << 5 |11:
  2472.       case 0x19 << 5 |12:
  2473.       case 0x19 << 5 |13:
  2474.       case 0x19 << 5 |14:
  2475.       case 0x19 << 5 |15:
  2476.       case 0x19 << 5 |16:
  2477.       case 0x19 << 5 |17:
  2478.       case 0x19 << 5 |18:
  2479.       case 0x19 << 5 |19:
  2480.       case 0x19 << 5 |20:
  2481.       case 0x19 << 5 |21:
  2482.       case 0x19 << 5 |22:
  2483.       case 0x19 << 5 |23:
  2484.       case 0x19 << 5 |24:
  2485.       case 0x19 << 5 |25:
  2486.       case 0x19 << 5 |26:
  2487.       case 0x19 << 5 |27:
  2488.       case 0x19 << 5 |28:
  2489.       case 0x19 << 5 |29:
  2490.       case 0x19 << 5 |30:
  2491.       case 0x19 << 5 |31:
  2492.          consume +=  isa_arm7_list_memory_access_load (agb, OP_code & 0xFF | (OP_code >>8 & 7) << 16, 0, 1, 0, 1);
  2493.          break;
  2494.       case 0xB4 << 2 | 0:
  2495.       case 0xB4 << 2 | 1:
  2496.       case 0xB4 << 2 | 2:
  2497.       case 0xB4 << 2 | 3:
  2498.          consume +=  isa_arm7_list_memory_access_store (agb, OP_code & 0xFF | 13 << 16, 1, 0, 0, 1);
  2499.          break;
  2500.       case 0xB5 << 2 | 0:
  2501.       case 0xB5 << 2 | 1:
  2502.       case 0xB5 << 2 | 2:
  2503.       case 0xB5 << 2 | 3:
  2504.          consume +=  isa_arm7_list_memory_access_store (agb, OP_code & 0xFF | 13 << 16 | 1 << 14, 1, 0, 0, 1);
  2505.          break;
  2506.       case 0xBC << 2 | 0:
  2507.       case 0xBC << 2 | 1:
  2508.       case 0xBC << 2 | 2:
  2509.       case 0xBC << 2 | 3:
  2510.          consume +=  isa_arm7_list_memory_access_load (agb, OP_code & 0xFF | 13 << 16, 0, 1, 0, 1);
  2511.          break;
  2512.       case 0xBD << 2 | 0:
  2513.       case 0xBD << 2 | 1:
  2514.       case 0xBD << 2 | 2:
  2515.       case 0xBD << 2 | 3:
  2516.          consume +=  isa_arm7_list_memory_access_load (agb, OP_code & 0xFF | 13 << 16 | 1 << 15, 0, 1, 0, 1);
  2517.          break;
  2518.       case 0xDF << 2 | 0:
  2519.       case 0xDF << 2 | 1:
  2520.       case 0xDF << 2 | 2:
  2521.       case 0xDF << 2 | 3:
  2522.         consume += isa_thumb_swi (agb, OP_code & 0xFF);
  2523.         break;
  2524.       case 0xB0 << 2 | 0:
  2525.       case 0xB0 << 2 | 1:
  2526.         regs[13] += (OP_code & 0x7F) * 4;
  2527.         consume++;
  2528.         break;
  2529.       case 0xB0 << 2 | 2:
  2530.       case 0xB0 << 2 | 3:
  2531.         regs[13] -= (OP_code & 0x7F) * 4;
  2532.         consume++;
  2533.         break;
  2534.  
  2535.       case 0x00 << 5 | 0:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 0, 0, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2536.       case 0x00 << 5 | 1:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 0, 1, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2537.       case 0x00 << 5 | 2:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 0, 2, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2538.       case 0x00 << 5 | 3:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 0, 3, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2539.       case 0x00 << 5 | 4:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 0, 4, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2540.       case 0x00 << 5 | 5:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 0, 5, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2541.       case 0x00 << 5 | 6:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 0, 6, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2542.       case 0x00 << 5 | 7:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 0, 7, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2543.       case 0x00 << 5 | 8:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 0, 8, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2544.       case 0x00 << 5 | 9:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 0, 9, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2545.       case 0x00 << 5 |10:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 0,10, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2546.       case 0x00 << 5 |11:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 0,11, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2547.       case 0x00 << 5 |12:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 0,12, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2548.       case 0x00 << 5 |13:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 0,13, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2549.       case 0x00 << 5 |14:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 0,14, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2550.       case 0x00 << 5 |15:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 0,15, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2551.       case 0x00 << 5 |16:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 0,16, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2552.       case 0x00 << 5 |17:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 0,17, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2553.       case 0x00 << 5 |18:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 0,18, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2554.       case 0x00 << 5 |19:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 0,19, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2555.       case 0x00 << 5 |20:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 0,20, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2556.       case 0x00 << 5 |21:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 0,21, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2557.       case 0x00 << 5 |22:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 0,22, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2558.       case 0x00 << 5 |23:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 0,23, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2559.       case 0x00 << 5 |24:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 0,24, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2560.       case 0x00 << 5 |25:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 0,25, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2561.       case 0x00 << 5 |26:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 0,26, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2562.       case 0x00 << 5 |27:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 0,27, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2563.       case 0x00 << 5 |28:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 0,28, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2564.       case 0x00 << 5 |29:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 0,29, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2565.       case 0x00 << 5 |30:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 0,30, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2566.       case 0x00 << 5 |31:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 0,31, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2567.  
  2568.       case 0x01 << 5 | 0:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 1, 0, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2569.       case 0x01 << 5 | 1:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 1, 1, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2570.       case 0x01 << 5 | 2:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 1, 2, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2571.       case 0x01 << 5 | 3:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 1, 3, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2572.       case 0x01 << 5 | 4:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 1, 4, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2573.       case 0x01 << 5 | 5:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 1, 5, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2574.       case 0x01 << 5 | 6:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 1, 6, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2575.       case 0x01 << 5 | 7:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 1, 7, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2576.       case 0x01 << 5 | 8:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 1, 8, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2577.       case 0x01 << 5 | 9:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 1, 9, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2578.       case 0x01 << 5 |10:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 1,10, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2579.       case 0x01 << 5 |11:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 1,11, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2580.       case 0x01 << 5 |12:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 1,12, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2581.       case 0x01 << 5 |13:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 1,13, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2582.       case 0x01 << 5 |14:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 1,14, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2583.       case 0x01 << 5 |15:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 1,15, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2584.       case 0x01 << 5 |16:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 1,16, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2585.       case 0x01 << 5 |17:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 1,17, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2586.       case 0x01 << 5 |18:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 1,18, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2587.       case 0x01 << 5 |19:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 1,19, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2588.       case 0x01 << 5 |20:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 1,20, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2589.       case 0x01 << 5 |21:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 1,21, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2590.       case 0x01 << 5 |22:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 1,22, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2591.       case 0x01 << 5 |23:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 1,23, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2592.       case 0x01 << 5 |24:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 1,24, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2593.       case 0x01 << 5 |25:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 1,25, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2594.       case 0x01 << 5 |26:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 1,26, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2595.       case 0x01 << 5 |27:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 1,27, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2596.       case 0x01 << 5 |28:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 1,28, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2597.       case 0x01 << 5 |29:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 1,29, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2598.       case 0x01 << 5 |30:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 1,30, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2599.       case 0x01 << 5 |31:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 1,31, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2600.  
  2601.       case 0x02 << 5 | 0:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 2, 0, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2602.       case 0x02 << 5 | 1:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 2, 1, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2603.       case 0x02 << 5 | 2:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 2, 2, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2604.       case 0x02 << 5 | 3:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 2, 3, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2605.       case 0x02 << 5 | 4:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 2, 4, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2606.       case 0x02 << 5 | 5:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 2, 5, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2607.       case 0x02 << 5 | 6:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 2, 6, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2608.       case 0x02 << 5 | 7:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 2, 7, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2609.       case 0x02 << 5 | 8:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 2, 8, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2610.       case 0x02 << 5 | 9:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 2, 9, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2611.       case 0x02 << 5 |10:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 2,10, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2612.       case 0x02 << 5 |11:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 2,11, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2613.       case 0x02 << 5 |12:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 2,12, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2614.       case 0x02 << 5 |13:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 2,13, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2615.       case 0x02 << 5 |14:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 2,14, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2616.       case 0x02 << 5 |15:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 2,15, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2617.       case 0x02 << 5 |16:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 2,16, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2618.       case 0x02 << 5 |17:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 2,17, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2619.       case 0x02 << 5 |18:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 2,18, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2620.       case 0x02 << 5 |19:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 2,19, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2621.       case 0x02 << 5 |20:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 2,20, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2622.       case 0x02 << 5 |21:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 2,21, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2623.       case 0x02 << 5 |22:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 2,22, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2624.       case 0x02 << 5 |23:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 2,23, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2625.       case 0x02 << 5 |24:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 2,24, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2626.       case 0x02 << 5 |25:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 2,25, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2627.       case 0x02 << 5 |26:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 2,26, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2628.       case 0x02 << 5 |27:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 2,27, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2629.       case 0x02 << 5 |28:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 2,28, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2630.       case 0x02 << 5 |29:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 2,29, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2631.       case 0x02 << 5 |30:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 2,30, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2632.       case 0x02 << 5 |31:  { uint32_t carry = arm->cpsr.c;  regs[OP_code & 7] = arm7_alu_shift_imm5 (arm, regs[OP_code >> 3 & 7], 2,31, & carry); update_flags_logic (arm, carry, regs[OP_code & 7], 0, 0, 0); consume ++; } break;
  2633.  
  2634.       case 0x03 << 5 | 0: isa_thumb_add (agb, regs[0], regs[OP_code >> 3 & 7], OP_code & 7);    consume ++;  break;
  2635.       case 0x03 << 5 | 1: isa_thumb_add (agb, regs[1], regs[OP_code >> 3 & 7], OP_code & 7);    consume ++;  break;
  2636.       case 0x03 << 5 | 2: isa_thumb_add (agb, regs[2], regs[OP_code >> 3 & 7], OP_code & 7);    consume ++;  break;
  2637.       case 0x03 << 5 | 3: isa_thumb_add (agb, regs[3], regs[OP_code >> 3 & 7], OP_code & 7);    consume ++;  break;
  2638.       case 0x03 << 5 | 4: isa_thumb_add (agb, regs[4], regs[OP_code >> 3 & 7], OP_code & 7);    consume ++;  break;
  2639.       case 0x03 << 5 | 5: isa_thumb_add (agb, regs[5], regs[OP_code >> 3 & 7], OP_code & 7);    consume ++;  break;
  2640.       case 0x03 << 5 | 6: isa_thumb_add (agb, regs[6], regs[OP_code >> 3 & 7], OP_code & 7);    consume ++;  break;
  2641.       case 0x03 << 5 | 7: isa_thumb_add (agb, regs[7], regs[OP_code >> 3 & 7], OP_code & 7);    consume ++;  break;
  2642.  
  2643.       case 0x03 << 5 | 8: isa_thumb_sub (agb, regs[0], regs[OP_code >> 3 & 7], OP_code & 7);    consume ++;  break;
  2644.       case 0x03 << 5 | 9: isa_thumb_sub (agb, regs[1], regs[OP_code >> 3 & 7], OP_code & 7);    consume ++;  break;
  2645.       case 0x03 << 5 |10: isa_thumb_sub (agb, regs[2], regs[OP_code >> 3 & 7], OP_code & 7);    consume ++;  break;
  2646.       case 0x03 << 5 |11: isa_thumb_sub (agb, regs[3], regs[OP_code >> 3 & 7], OP_code & 7);    consume ++;  break;
  2647.       case 0x03 << 5 |12: isa_thumb_sub (agb, regs[4], regs[OP_code >> 3 & 7], OP_code & 7);    consume ++;  break;
  2648.       case 0x03 << 5 |13: isa_thumb_sub (agb, regs[5], regs[OP_code >> 3 & 7], OP_code & 7);    consume ++;  break;
  2649.       case 0x03 << 5 |14: isa_thumb_sub (agb, regs[6], regs[OP_code >> 3 & 7], OP_code & 7);    consume ++;  break;
  2650.       case 0x03 << 5 |15: isa_thumb_sub (agb, regs[7], regs[OP_code >> 3 & 7], OP_code & 7);    consume ++;  break;
  2651.  
  2652.       case 0x03 << 5 |16: isa_thumb_add (agb, 0, regs[OP_code >> 3 & 7], OP_code & 7);    consume ++;  break;
  2653.       case 0x03 << 5 |17: isa_thumb_add (agb, 1, regs[OP_code >> 3 & 7], OP_code & 7);    consume ++;  break;
  2654.       case 0x03 << 5 |18: isa_thumb_add (agb, 2, regs[OP_code >> 3 & 7], OP_code & 7);    consume ++;  break;
  2655.       case 0x03 << 5 |19: isa_thumb_add (agb, 3, regs[OP_code >> 3 & 7], OP_code & 7);    consume ++;  break;
  2656.       case 0x03 << 5 |20: isa_thumb_add (agb, 4, regs[OP_code >> 3 & 7], OP_code & 7);    consume ++;  break;
  2657.       case 0x03 << 5 |21: isa_thumb_add (agb, 5, regs[OP_code >> 3 & 7], OP_code & 7);    consume ++;  break;
  2658.       case 0x03 << 5 |22: isa_thumb_add (agb, 6, regs[OP_code >> 3 & 7], OP_code & 7);    consume ++;  break;
  2659.       case 0x03 << 5 |23: isa_thumb_add (agb, 7, regs[OP_code >> 3 & 7], OP_code & 7);    consume ++;  break;
  2660.  
  2661.       case 0x03 << 5 |24: isa_thumb_sub (agb, 0, regs[OP_code >> 3 & 7], OP_code & 7);    consume ++;  break;
  2662.       case 0x03 << 5 |25: isa_thumb_sub (agb, 1, regs[OP_code >> 3 & 7], OP_code & 7);    consume ++;  break;
  2663.       case 0x03 << 5 |26: isa_thumb_sub (agb, 2, regs[OP_code >> 3 & 7], OP_code & 7);    consume ++;  break;
  2664.       case 0x03 << 5 |27: isa_thumb_sub (agb, 3, regs[OP_code >> 3 & 7], OP_code & 7);    consume ++;  break;
  2665.       case 0x03 << 5 |28: isa_thumb_sub (agb, 4, regs[OP_code >> 3 & 7], OP_code & 7);    consume ++;  break;
  2666.       case 0x03 << 5 |29: isa_thumb_sub (agb, 5, regs[OP_code >> 3 & 7], OP_code & 7);    consume ++;  break;
  2667.       case 0x03 << 5 |30: isa_thumb_sub (agb, 6, regs[OP_code >> 3 & 7], OP_code & 7);    consume ++;  break;
  2668.       case 0x03 << 5 |31: isa_thumb_sub (agb, 7, regs[OP_code >> 3 & 7], OP_code & 7);    consume ++;  break;
  2669.  
  2670. #define MCAS_CASE(n) \
  2671.       case 0x04 << 5 | (n) * 4 + 0:\
  2672.       case 0x04 << 5 | (n) * 4 + 1:\
  2673.       case 0x04 << 5 | (n) * 4 + 2:\
  2674.       case 0x04 << 5 | (n) * 4 + 3: regs[n] = OP_code & 255; update_flags_logic_fast (arm, OP_code & 255); consume ++; break;\
  2675.       case 0x05 << 5 | (n) * 4 + 0:\
  2676.       case 0x05 << 5 | (n) * 4 + 1:\
  2677.       case 0x05 << 5 | (n) * 4 + 2:\
  2678.       case 0x05 << 5 | (n) * 4 + 3: isa_thumb_cmp (agb, OP_code & 255, regs[n]);    consume ++;  break; \
  2679.       case 0x06 << 5 | (n) * 4 + 0:\
  2680.       case 0x06 << 5 | (n) * 4 + 1:\
  2681.       case 0x06 << 5 | (n) * 4 + 2:\
  2682.       case 0x06 << 5 | (n) * 4 + 3: isa_thumb_add (agb, OP_code & 255, regs[n], n);    consume ++;  break; \
  2683.       case 0x07 << 5 | (n) * 4 + 0:\
  2684.       case 0x07 << 5 | (n) * 4 + 1:\
  2685.       case 0x07 << 5 | (n) * 4 + 2:\
  2686.       case 0x07 << 5 | (n) * 4 + 3: isa_thumb_sub (agb, OP_code & 255, regs[n], n);    consume ++;  break;
  2687.  
  2688.       MCAS_CASE (0)
  2689.       MCAS_CASE (1)
  2690.       MCAS_CASE (2)
  2691.       MCAS_CASE (3)
  2692.       MCAS_CASE (4)
  2693.       MCAS_CASE (5)
  2694.       MCAS_CASE (6)
  2695.       MCAS_CASE (7)
  2696.  
  2697.       case 0x08 << 5 |16:
  2698.       case 0x08 << 5 |17:
  2699.       case 0x08 << 5 |18:
  2700.       case 0x08 << 5 |19:
  2701.         {
  2702.           const uint32_t rm = OP_code >> 3 & 15;
  2703.           const uint32_t rn_rd = OP_code & 7 | (OP_code >> 7 & 1) << 3;
  2704.           regs[rn_rd] += regs[rm];
  2705.           if  (rn_rd == 15) {
  2706.             regs[rn_rd] &= THUMB_CODE_MASK; /* FIXME: and -4 ?? */
  2707.             consume += thumb_flush (agb) + 3;
  2708.           } else
  2709.             consume += 1;
  2710.         }
  2711.         break;
  2712.  
  2713.       case 0x08 << 5 |20:
  2714.       case 0x08 << 5 |21:
  2715.       case 0x08 << 5 |22:
  2716.       case 0x08 << 5 |23:
  2717.         {
  2718.           const uint32_t rm = OP_code >> 3 & 15;
  2719.           const uint32_t rn_rd = OP_code & 7 | (OP_code >> 7 & 1) << 3;
  2720.           isa_thumb_cmp (agb, regs[rm], regs[rn_rd]);
  2721.           consume ++;
  2722.         }
  2723.         break;
  2724.  
  2725.       case 0x08 << 5 |24:
  2726.       case 0x08 << 5 |25:
  2727.       case 0x08 << 5 |26:
  2728.       case 0x08 << 5 |27:
  2729.         {
  2730.           const uint32_t rm = OP_code >> 3 & 15;
  2731.           const uint32_t rn_rd = OP_code & 7 | (OP_code >> 7 & 1) << 3;
  2732.           regs[rn_rd] = regs[rm];
  2733.  
  2734.           if  (rn_rd == 15) {
  2735.             regs[rn_rd] &= THUMB_CODE_MASK; /* FIXME: and -4 ?? */
  2736.             consume += thumb_flush (agb) + 3;
  2737.           } else
  2738.             consume += 1;
  2739.  
  2740.           consume ++;
  2741.         }
  2742.         break;
  2743.  
  2744.       case 0x08 << 5 |28:
  2745.       case 0x08 << 5 |29:
  2746.       case 0x08 << 5 |30:
  2747.       case 0x08 << 5 |31:
  2748.         {
  2749.           const uint32_t rm = OP_code >> 3 & 15;
  2750.           const uint32_t thumb = regs[rm] & 1;
  2751.           const uint32_t pc = regs[rm] & THUMB_CODE_MASK;
  2752.           arm->cpsr.thumb = thumb;
  2753.           if (thumb != 0) {
  2754.             regs[15] = pc;
  2755.             consume += thumb_flush (agb) + 3;
  2756.           } else {
  2757.             const uint32_t temp_pc = pc & ARM7_CODE_MASK;
  2758.             regs[15] = temp_pc;
  2759.             consume += arm7_flush (agb) + 3;
  2760.             regs[15] = temp_pc + 8 - 2;
  2761.           }
  2762.         }
  2763.         break;
  2764.  
  2765.       case 0x09 << 5 | 0: consume += isa_thumb_ldr_pc (agb, 0 >> 2, OP_code & 0xFF); break;
  2766.       case 0x09 << 5 | 1: consume += isa_thumb_ldr_pc (agb, 1 >> 2, OP_code & 0xFF);  break;
  2767.       case 0x09 << 5 | 2: consume += isa_thumb_ldr_pc (agb, 2 >> 2, OP_code & 0xFF);  break;
  2768.       case 0x09 << 5 | 3: consume += isa_thumb_ldr_pc (agb, 3 >> 2, OP_code & 0xFF);  break;
  2769.       case 0x09 << 5 | 4: consume += isa_thumb_ldr_pc (agb, 4 >> 2, OP_code & 0xFF);  break;
  2770.       case 0x09 << 5 | 5: consume += isa_thumb_ldr_pc (agb, 5 >> 2, OP_code & 0xFF);  break;
  2771.       case 0x09 << 5 | 6: consume += isa_thumb_ldr_pc (agb, 6 >> 2, OP_code & 0xFF);  break;
  2772.       case 0x09 << 5 | 7: consume += isa_thumb_ldr_pc (agb, 7 >> 2, OP_code & 0xFF);  break;
  2773.       case 0x09 << 5 | 8: consume += isa_thumb_ldr_pc (agb, 8 >> 2, OP_code & 0xFF);  break;
  2774.       case 0x09 << 5 | 9: consume += isa_thumb_ldr_pc (agb, 9 >> 2, OP_code & 0xFF);  break;
  2775.       case 0x09 << 5 |10: consume += isa_thumb_ldr_pc (agb, 10 >> 2, OP_code & 0xFF);  break;
  2776.       case 0x09 << 5 |11: consume += isa_thumb_ldr_pc (agb, 11 >> 2, OP_code & 0xFF);  break;
  2777.       case 0x09 << 5 |12: consume += isa_thumb_ldr_pc (agb, 12 >> 2, OP_code & 0xFF);  break;
  2778.       case 0x09 << 5 |13: consume += isa_thumb_ldr_pc (agb, 13 >> 2, OP_code & 0xFF);  break;
  2779.       case 0x09 << 5 |14: consume += isa_thumb_ldr_pc (agb, 14 >> 2, OP_code & 0xFF);  break;
  2780.       case 0x09 << 5 |15: consume += isa_thumb_ldr_pc (agb, 15 >> 2, OP_code & 0xFF);  break;
  2781.       case 0x09 << 5 |16: consume += isa_thumb_ldr_pc (agb, 16 >> 2, OP_code & 0xFF);  break;
  2782.       case 0x09 << 5 |17: consume += isa_thumb_ldr_pc (agb, 17 >> 2, OP_code & 0xFF);  break;
  2783.       case 0x09 << 5 |18: consume += isa_thumb_ldr_pc (agb, 18 >> 2, OP_code & 0xFF);  break;
  2784.       case 0x09 << 5 |19: consume += isa_thumb_ldr_pc (agb, 19 >> 2, OP_code & 0xFF);  break;
  2785.       case 0x09 << 5 |20: consume += isa_thumb_ldr_pc (agb, 20 >> 2, OP_code & 0xFF);  break;
  2786.       case 0x09 << 5 |21: consume += isa_thumb_ldr_pc (agb, 21 >> 2, OP_code & 0xFF);  break;
  2787.       case 0x09 << 5 |22: consume += isa_thumb_ldr_pc (agb, 22 >> 2, OP_code & 0xFF);  break;
  2788.       case 0x09 << 5 |23: consume += isa_thumb_ldr_pc (agb, 23 >> 2, OP_code & 0xFF);  break;
  2789.       case 0x09 << 5 |24: consume += isa_thumb_ldr_pc (agb, 24 >> 2, OP_code & 0xFF);  break;
  2790.       case 0x09 << 5 |25: consume += isa_thumb_ldr_pc (agb, 25 >> 2, OP_code & 0xFF);  break;
  2791.       case 0x09 << 5 |26: consume += isa_thumb_ldr_pc (agb, 26 >> 2, OP_code & 0xFF);  break;
  2792.       case 0x09 << 5 |27: consume += isa_thumb_ldr_pc (agb, 27 >> 2, OP_code & 0xFF);  break;
  2793.       case 0x09 << 5 |28: consume += isa_thumb_ldr_pc (agb, 28 >> 2, OP_code & 0xFF);  break;
  2794.       case 0x09 << 5 |29: consume += isa_thumb_ldr_pc (agb, 29 >> 2, OP_code & 0xFF);  break;
  2795.       case 0x09 << 5 |30: consume += isa_thumb_ldr_pc (agb, 30 >> 2, OP_code & 0xFF);  break;
  2796.       case 0x09 << 5 |31: consume += isa_thumb_ldr_pc (agb, 31 >> 2, OP_code & 0xFF);  break;
  2797.        
  2798.       case 0x0A << 5 | 1 << 3 | 0: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 0, 0, 1, OP_code >> 3 & 7, OP_code & 7, regs[0]); break;
  2799.       case 0x0A << 5 | 1 << 3 | 1: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 0, 0, 1,  OP_code >> 3 & 7, OP_code & 7, regs[1]); break;
  2800.       case 0x0A << 5 | 1 << 3 | 2: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 0, 0, 1,  OP_code >> 3 & 7, OP_code & 7, regs[2]); break;
  2801.       case 0x0A << 5 | 1 << 3 | 3: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 0, 0, 1,  OP_code >> 3 & 7, OP_code & 7, regs[3]); break;
  2802.       case 0x0A << 5 | 1 << 3 | 4: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 0, 0, 1,  OP_code >> 3 & 7, OP_code & 7, regs[4]); break;
  2803.       case 0x0A << 5 | 1 << 3 | 5: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 0, 0, 1,  OP_code >> 3 & 7, OP_code & 7, regs[5]); break;
  2804.       case 0x0A << 5 | 1 << 3 | 6: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 0, 0, 1,  OP_code >> 3 & 7, OP_code & 7, regs[6]); break;
  2805.       case 0x0A << 5 | 1 << 3 | 7: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 0, 0, 1,  OP_code >> 3 & 7, OP_code & 7, regs[7]); break;
  2806.      
  2807.       case 0x0A << 5 | 3 << 3 | 0: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 1, 1, 0, OP_code >> 3 & 7, OP_code & 7, regs[0]); break;
  2808.       case 0x0A << 5 | 3 << 3 | 1: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 1, 1, 0, OP_code >> 3 & 7, OP_code & 7, regs[1]); break;
  2809.       case 0x0A << 5 | 3 << 3 | 2: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 1, 1, 0, OP_code >> 3 & 7, OP_code & 7, regs[2]); break;
  2810.       case 0x0A << 5 | 3 << 3 | 3: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 1, 1, 0, OP_code >> 3 & 7, OP_code & 7, regs[3]); break;
  2811.       case 0x0A << 5 | 3 << 3 | 4: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 1, 1, 0, OP_code >> 3 & 7, OP_code & 7, regs[4]); break;
  2812.       case 0x0A << 5 | 3 << 3 | 5: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 1, 1, 0, OP_code >> 3 & 7, OP_code & 7, regs[5]); break;
  2813.       case 0x0A << 5 | 3 << 3 | 6: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 1, 1, 0, OP_code >> 3 & 7, OP_code & 7, regs[6]); break;
  2814.       case 0x0A << 5 | 3 << 3 | 7: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 1, 1, 0, OP_code >> 3 & 7, OP_code & 7, regs[7]); break;
  2815.      
  2816.       case 0x0B << 5 | 1 << 3 | 0: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 1, 0, 1, OP_code >> 3 & 7, OP_code & 7, regs[0]); break;
  2817.       case 0x0B << 5 | 1 << 3 | 1: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 1, 0, 1, OP_code >> 3 & 7, OP_code & 7, regs[1]); break;
  2818.       case 0x0B << 5 | 1 << 3 | 2: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 1, 0, 1, OP_code >> 3 & 7, OP_code & 7, regs[2]); break;
  2819.       case 0x0B << 5 | 1 << 3 | 3: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 1, 0, 1, OP_code >> 3 & 7, OP_code & 7, regs[3]); break;
  2820.       case 0x0B << 5 | 1 << 3 | 4: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 1, 0, 1, OP_code >> 3 & 7, OP_code & 7, regs[4]); break;
  2821.       case 0x0B << 5 | 1 << 3 | 5: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 1, 0, 1, OP_code >> 3 & 7, OP_code & 7, regs[5]); break;
  2822.       case 0x0B << 5 | 1 << 3 | 6: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 1, 0, 1, OP_code >> 3 & 7, OP_code & 7, regs[6]); break;
  2823.       case 0x0B << 5 | 1 << 3 | 7: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 1, 0, 1, OP_code >> 3 & 7, OP_code & 7, regs[7]); break;
  2824.      
  2825.       case 0x0B << 5 | 3 << 3 | 0: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 1, 1, 1, OP_code >> 3 & 7, OP_code & 7, regs[0]); break;
  2826.       case 0x0B << 5 | 3 << 3 | 1: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 1, 1, 1, OP_code >> 3 & 7, OP_code & 7, regs[1]); break;
  2827.       case 0x0B << 5 | 3 << 3 | 2: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 1, 1, 1, OP_code >> 3 & 7, OP_code & 7, regs[2]); break;
  2828.       case 0x0B << 5 | 3 << 3 | 3: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 1, 1, 1, OP_code >> 3 & 7, OP_code & 7, regs[3]); break;
  2829.       case 0x0B << 5 | 3 << 3 | 4: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 1, 1, 1, OP_code >> 3 & 7, OP_code & 7, regs[4]); break;
  2830.       case 0x0B << 5 | 3 << 3 | 5: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 1, 1, 1, OP_code >> 3 & 7, OP_code & 7, regs[5]); break;
  2831.       case 0x0B << 5 | 3 << 3 | 6: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 1, 1, 1, OP_code >> 3 & 7, OP_code & 7, regs[6]); break;
  2832.       case 0x0B << 5 | 3 << 3 | 7: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 1, 1, 1, OP_code >> 3 & 7, OP_code & 7, regs[7]); break;
  2833.  
  2834.       case 0x0A << 5 | 0 << 3 | 0: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 0, OP_code >> 3 & 7, OP_code & 7, regs[0]); break;
  2835.       case 0x0A << 5 | 0 << 3 | 1: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 0, OP_code >> 3 & 7, OP_code & 7, regs[1]); break;
  2836.       case 0x0A << 5 | 0 << 3 | 2: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 0, OP_code >> 3 & 7, OP_code & 7, regs[2]); break;
  2837.       case 0x0A << 5 | 0 << 3 | 3: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 0, OP_code >> 3 & 7, OP_code & 7, regs[3]); break;
  2838.       case 0x0A << 5 | 0 << 3 | 4: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 0, OP_code >> 3 & 7, OP_code & 7, regs[4]); break;
  2839.       case 0x0A << 5 | 0 << 3 | 5: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 0, OP_code >> 3 & 7, OP_code & 7, regs[5]); break;
  2840.       case 0x0A << 5 | 0 << 3 | 6: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 0, OP_code >> 3 & 7, OP_code & 7, regs[6]); break;
  2841.       case 0x0A << 5 | 0 << 3 | 7: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 0, OP_code >> 3 & 7, OP_code & 7, regs[7]); break;
  2842.      
  2843.       case 0x0A << 5 | 2 << 3 | 0: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 1, 0, 0, OP_code >> 3 & 7, OP_code & 7, regs[0]); break;
  2844.       case 0x0A << 5 | 2 << 3 | 1: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 1, 0, 0, OP_code >> 3 & 7, OP_code & 7, regs[1]); break;
  2845.       case 0x0A << 5 | 2 << 3 | 2: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 1, 0, 0, OP_code >> 3 & 7, OP_code & 7, regs[2]); break;
  2846.       case 0x0A << 5 | 2 << 3 | 3: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 1, 0, 0, OP_code >> 3 & 7, OP_code & 7, regs[3]); break;
  2847.       case 0x0A << 5 | 2 << 3 | 4: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 1, 0, 0, OP_code >> 3 & 7, OP_code & 7, regs[4]); break;
  2848.       case 0x0A << 5 | 2 << 3 | 5: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 1, 0, 0, OP_code >> 3 & 7, OP_code & 7, regs[5]); break;
  2849.       case 0x0A << 5 | 2 << 3 | 6: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 1, 0, 0, OP_code >> 3 & 7, OP_code & 7, regs[6]); break;
  2850.       case 0x0A << 5 | 2 << 3 | 7: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 1, 0, 0, OP_code >> 3 & 7, OP_code & 7, regs[7]); break;
  2851.      
  2852.       case 0x0B << 5 | 0 << 3 | 0: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 1, OP_code >> 3 & 7, OP_code & 7, regs[0]); break;
  2853.       case 0x0B << 5 | 0 << 3 | 1: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 1, OP_code >> 3 & 7, OP_code & 7, regs[1]); break;
  2854.       case 0x0B << 5 | 0 << 3 | 2: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 1, OP_code >> 3 & 7, OP_code & 7, regs[2]); break;
  2855.       case 0x0B << 5 | 0 << 3 | 3: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 1, OP_code >> 3 & 7, OP_code & 7, regs[3]); break;
  2856.       case 0x0B << 5 | 0 << 3 | 4: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 1, OP_code >> 3 & 7, OP_code & 7, regs[4]); break;
  2857.       case 0x0B << 5 | 0 << 3 | 5: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 1, OP_code >> 3 & 7, OP_code & 7, regs[5]); break;
  2858.       case 0x0B << 5 | 0 << 3 | 6: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 1, OP_code >> 3 & 7, OP_code & 7, regs[6]); break;
  2859.       case 0x0B << 5 | 0 << 3 | 7: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 1, OP_code >> 3 & 7, OP_code & 7, regs[7]); break;
  2860.      
  2861.       case 0x0B << 5 | 2 << 3 | 0: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 1, 0, 1, OP_code >> 3 & 7, OP_code & 7, regs[0]); break;
  2862.       case 0x0B << 5 | 2 << 3 | 1: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 1, 0, 1, OP_code >> 3 & 7, OP_code & 7, regs[1]); break;
  2863.       case 0x0B << 5 | 2 << 3 | 2: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 1, 0, 1, OP_code >> 3 & 7, OP_code & 7, regs[2]); break;
  2864.       case 0x0B << 5 | 2 << 3 | 3: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 1, 0, 1, OP_code >> 3 & 7, OP_code & 7, regs[3]); break;
  2865.       case 0x0B << 5 | 2 << 3 | 4: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 1, 0, 1, OP_code >> 3 & 7, OP_code & 7, regs[4]); break;
  2866.       case 0x0B << 5 | 2 << 3 | 5: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 1, 0, 1, OP_code >> 3 & 7, OP_code & 7, regs[5]); break;
  2867.       case 0x0B << 5 | 2 << 3 | 6: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 1, 0, 1, OP_code >> 3 & 7, OP_code & 7, regs[6]); break;
  2868.       case 0x0B << 5 | 2 << 3 | 7: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 1, 0, 1, OP_code >> 3 & 7, OP_code & 7, regs[7]); break;
  2869.  
  2870.       case 0x0C << 5 | 0: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 0, OP_code >> 3 & 7, OP_code & 7, 0 * 4); break;
  2871.       case 0x0C << 5 | 1: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 0, OP_code >> 3 & 7, OP_code & 7, 1 * 4); break;
  2872.       case 0x0C << 5 | 2: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 0, OP_code >> 3 & 7, OP_code & 7, 2 * 4); break;
  2873.       case 0x0C << 5 | 3: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 0, OP_code >> 3 & 7, OP_code & 7, 3 * 4); break;
  2874.       case 0x0C << 5 | 4: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 0, OP_code >> 3 & 7, OP_code & 7, 4 * 4); break;
  2875.       case 0x0C << 5 | 5: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 0, OP_code >> 3 & 7, OP_code & 7, 5 * 4); break;
  2876.       case 0x0C << 5 | 6: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 0, OP_code >> 3 & 7, OP_code & 7, 6 * 4); break;
  2877.       case 0x0C << 5 | 7: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 0, OP_code >> 3 & 7, OP_code & 7, 7 * 4); break;
  2878.       case 0x0C << 5 | 8: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 0, OP_code >> 3 & 7, OP_code & 7, 8 * 4); break;
  2879.       case 0x0C << 5 | 9: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 0, OP_code >> 3 & 7, OP_code & 7, 9 * 4); break;
  2880.       case 0x0C << 5 |10: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 0, OP_code >> 3 & 7, OP_code & 7, 10 * 4); break;
  2881.       case 0x0C << 5 |11: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 0, OP_code >> 3 & 7, OP_code & 7, 11 * 4); break;
  2882.       case 0x0C << 5 |12: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 0, OP_code >> 3 & 7, OP_code & 7, 12 * 4); break;
  2883.       case 0x0C << 5 |13: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 0, OP_code >> 3 & 7, OP_code & 7, 13 * 4); break;
  2884.       case 0x0C << 5 |14: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 0, OP_code >> 3 & 7, OP_code & 7, 14 * 4); break;
  2885.       case 0x0C << 5 |15: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 0, OP_code >> 3 & 7, OP_code & 7, 15 * 4); break;
  2886.       case 0x0C << 5 |16: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 0, OP_code >> 3 & 7, OP_code & 7, 16 * 4); break;
  2887.       case 0x0C << 5 |17: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 0, OP_code >> 3 & 7, OP_code & 7, 17 * 4); break;
  2888.       case 0x0C << 5 |18: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 0, OP_code >> 3 & 7, OP_code & 7, 18 * 4); break;
  2889.       case 0x0C << 5 |19: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 0, OP_code >> 3 & 7, OP_code & 7, 19 * 4); break;
  2890.       case 0x0C << 5 |20: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 0, OP_code >> 3 & 7, OP_code & 7, 20 * 4); break;
  2891.       case 0x0C << 5 |21: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 0, OP_code >> 3 & 7, OP_code & 7, 21 * 4); break;
  2892.       case 0x0C << 5 |22: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 0, OP_code >> 3 & 7, OP_code & 7, 22 * 4); break;
  2893.       case 0x0C << 5 |23: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 0, OP_code >> 3 & 7, OP_code & 7, 23 * 4); break;
  2894.       case 0x0C << 5 |24: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 0, OP_code >> 3 & 7, OP_code & 7, 24 * 4); break;
  2895.       case 0x0C << 5 |25: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 0, OP_code >> 3 & 7, OP_code & 7, 25 * 4); break;
  2896.       case 0x0C << 5 |26: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 0, OP_code >> 3 & 7, OP_code & 7, 26 * 4); break;
  2897.       case 0x0C << 5 |27: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 0, OP_code >> 3 & 7, OP_code & 7, 27 * 4); break;
  2898.       case 0x0C << 5 |28: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 0, OP_code >> 3 & 7, OP_code & 7, 28 * 4); break;
  2899.       case 0x0C << 5 |29: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 0, OP_code >> 3 & 7, OP_code & 7, 29 * 4); break;
  2900.       case 0x0C << 5 |30: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 0, OP_code >> 3 & 7, OP_code & 7, 30 * 4); break;
  2901.       case 0x0C << 5 |31: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 0, OP_code >> 3 & 7, OP_code & 7, 31 * 4); break;
  2902.  
  2903.       case 0x0D << 5 | 0: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 1, OP_code >> 3 & 7, OP_code & 7, 0 * 4); break;
  2904.       case 0x0D << 5 | 1: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 1, OP_code >> 3 & 7, OP_code & 7, 1 * 4); break;
  2905.       case 0x0D << 5 | 2: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 1, OP_code >> 3 & 7, OP_code & 7, 2 * 4); break;
  2906.       case 0x0D << 5 | 3: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 1, OP_code >> 3 & 7, OP_code & 7, 3 * 4); break;
  2907.       case 0x0D << 5 | 4: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 1, OP_code >> 3 & 7, OP_code & 7, 4 * 4); break;
  2908.       case 0x0D << 5 | 5: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 1, OP_code >> 3 & 7, OP_code & 7, 5 * 4); break;
  2909.       case 0x0D << 5 | 6: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 1, OP_code >> 3 & 7, OP_code & 7, 6 * 4); break;
  2910.       case 0x0D << 5 | 7: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 1, OP_code >> 3 & 7, OP_code & 7, 7 * 4); break;
  2911.       case 0x0D << 5 | 8: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 1, OP_code >> 3 & 7, OP_code & 7, 8 * 4); break;
  2912.       case 0x0D << 5 | 9: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 1, OP_code >> 3 & 7, OP_code & 7, 9 * 4); break;
  2913.       case 0x0D << 5 |10: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 1, OP_code >> 3 & 7, OP_code & 7, 10 * 4); break;
  2914.       case 0x0D << 5 |11: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 1, OP_code >> 3 & 7, OP_code & 7, 11 * 4); break;
  2915.       case 0x0D << 5 |12: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 1, OP_code >> 3 & 7, OP_code & 7, 12 * 4); break;
  2916.       case 0x0D << 5 |13: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 1, OP_code >> 3 & 7, OP_code & 7, 13 * 4); break;
  2917.       case 0x0D << 5 |14: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 1, OP_code >> 3 & 7, OP_code & 7, 14 * 4); break;
  2918.       case 0x0D << 5 |15: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 1, OP_code >> 3 & 7, OP_code & 7, 15 * 4); break;
  2919.       case 0x0D << 5 |16: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 1, OP_code >> 3 & 7, OP_code & 7, 16 * 4); break;
  2920.       case 0x0D << 5 |17: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 1, OP_code >> 3 & 7, OP_code & 7, 17 * 4); break;
  2921.       case 0x0D << 5 |18: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 1, OP_code >> 3 & 7, OP_code & 7, 18 * 4); break;
  2922.       case 0x0D << 5 |19: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 1, OP_code >> 3 & 7, OP_code & 7, 19 * 4); break;
  2923.       case 0x0D << 5 |20: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 1, OP_code >> 3 & 7, OP_code & 7, 20 * 4); break;
  2924.       case 0x0D << 5 |21: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 1, OP_code >> 3 & 7, OP_code & 7, 21 * 4); break;
  2925.       case 0x0D << 5 |22: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 1, OP_code >> 3 & 7, OP_code & 7, 22 * 4); break;
  2926.       case 0x0D << 5 |23: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 1, OP_code >> 3 & 7, OP_code & 7, 23 * 4); break;
  2927.       case 0x0D << 5 |24: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 1, OP_code >> 3 & 7, OP_code & 7, 24 * 4); break;
  2928.       case 0x0D << 5 |25: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 1, OP_code >> 3 & 7, OP_code & 7, 25 * 4); break;
  2929.       case 0x0D << 5 |26: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 1, OP_code >> 3 & 7, OP_code & 7, 26 * 4); break;
  2930.       case 0x0D << 5 |27: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 1, OP_code >> 3 & 7, OP_code & 7, 27 * 4); break;
  2931.       case 0x0D << 5 |28: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 1, OP_code >> 3 & 7, OP_code & 7, 28 * 4); break;
  2932.       case 0x0D << 5 |29: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 1, OP_code >> 3 & 7, OP_code & 7, 29 * 4); break;
  2933.       case 0x0D << 5 |30: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 1, OP_code >> 3 & 7, OP_code & 7, 30 * 4); break;
  2934.       case 0x0D << 5 |31: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 1, OP_code >> 3 & 7, OP_code & 7, 31 * 4); break;
  2935.  
  2936.       case 0x0E << 5 | 0: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 1, 0, 0, OP_code >> 3 & 7, OP_code & 7, 0); break;
  2937.       case 0x0E << 5 | 1: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 1, 0, 0, OP_code >> 3 & 7, OP_code & 7, 1); break;
  2938.       case 0x0E << 5 | 2: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 1, 0, 0, OP_code >> 3 & 7, OP_code & 7, 2); break;
  2939.       case 0x0E << 5 | 3: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 1, 0, 0, OP_code >> 3 & 7, OP_code & 7, 3); break;
  2940.       case 0x0E << 5 | 4: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 1, 0, 0, OP_code >> 3 & 7, OP_code & 7, 4); break;
  2941.       case 0x0E << 5 | 5: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 1, 0, 0, OP_code >> 3 & 7, OP_code & 7, 5); break;
  2942.       case 0x0E << 5 | 6: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 1, 0, 0, OP_code >> 3 & 7, OP_code & 7, 6); break;
  2943.       case 0x0E << 5 | 7: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 1, 0, 0, OP_code >> 3 & 7, OP_code & 7, 7); break;
  2944.       case 0x0E << 5 | 8: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 1, 0, 0, OP_code >> 3 & 7, OP_code & 7, 8); break;
  2945.       case 0x0E << 5 | 9: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 1, 0, 0, OP_code >> 3 & 7, OP_code & 7, 9); break;
  2946.       case 0x0E << 5 |10: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 1, 0, 0, OP_code >> 3 & 7, OP_code & 7, 10); break;
  2947.       case 0x0E << 5 |11: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 1, 0, 0, OP_code >> 3 & 7, OP_code & 7, 11); break;
  2948.       case 0x0E << 5 |12: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 1, 0, 0, OP_code >> 3 & 7, OP_code & 7, 12); break;
  2949.       case 0x0E << 5 |13: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 1, 0, 0, OP_code >> 3 & 7, OP_code & 7, 13); break;
  2950.       case 0x0E << 5 |14: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 1, 0, 0, OP_code >> 3 & 7, OP_code & 7, 14); break;
  2951.       case 0x0E << 5 |15: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 1, 0, 0, OP_code >> 3 & 7, OP_code & 7, 15); break;
  2952.       case 0x0E << 5 |16: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 1, 0, 0, OP_code >> 3 & 7, OP_code & 7, 16); break;
  2953.       case 0x0E << 5 |17: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 1, 0, 0, OP_code >> 3 & 7, OP_code & 7, 17); break;
  2954.       case 0x0E << 5 |18: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 1, 0, 0, OP_code >> 3 & 7, OP_code & 7, 18); break;
  2955.       case 0x0E << 5 |19: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 1, 0, 0, OP_code >> 3 & 7, OP_code & 7, 19); break;
  2956.       case 0x0E << 5 |20: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 1, 0, 0, OP_code >> 3 & 7, OP_code & 7, 20); break;
  2957.       case 0x0E << 5 |21: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 1, 0, 0, OP_code >> 3 & 7, OP_code & 7, 21); break;
  2958.       case 0x0E << 5 |22: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 1, 0, 0, OP_code >> 3 & 7, OP_code & 7, 22); break;
  2959.       case 0x0E << 5 |23: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 1, 0, 0, OP_code >> 3 & 7, OP_code & 7, 23); break;
  2960.       case 0x0E << 5 |24: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 1, 0, 0, OP_code >> 3 & 7, OP_code & 7, 24); break;
  2961.       case 0x0E << 5 |25: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 1, 0, 0, OP_code >> 3 & 7, OP_code & 7, 25); break;
  2962.       case 0x0E << 5 |26: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 1, 0, 0, OP_code >> 3 & 7, OP_code & 7, 26); break;
  2963.       case 0x0E << 5 |27: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 1, 0, 0, OP_code >> 3 & 7, OP_code & 7, 27); break;
  2964.       case 0x0E << 5 |28: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 1, 0, 0, OP_code >> 3 & 7, OP_code & 7, 28); break;
  2965.       case 0x0E << 5 |29: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 1, 0, 0, OP_code >> 3 & 7, OP_code & 7, 29); break;
  2966.       case 0x0E << 5 |30: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 1, 0, 0, OP_code >> 3 & 7, OP_code & 7, 30); break;
  2967.       case 0x0E << 5 |31: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 1, 0, 0, OP_code >> 3 & 7, OP_code & 7, 31); break;
  2968.  
  2969.       case 0x0F << 5 | 0: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 1, 0, 1, OP_code >> 3 & 7, OP_code & 7, 0); break;
  2970.       case 0x0F << 5 | 1: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 1, 0, 1, OP_code >> 3 & 7, OP_code & 7, 1); break;
  2971.       case 0x0F << 5 | 2: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 1, 0, 1, OP_code >> 3 & 7, OP_code & 7, 2); break;
  2972.       case 0x0F << 5 | 3: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 1, 0, 1, OP_code >> 3 & 7, OP_code & 7, 3); break;
  2973.       case 0x0F << 5 | 4: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 1, 0, 1, OP_code >> 3 & 7, OP_code & 7, 4); break;
  2974.       case 0x0F << 5 | 5: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 1, 0, 1, OP_code >> 3 & 7, OP_code & 7, 5); break;
  2975.       case 0x0F << 5 | 6: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 1, 0, 1, OP_code >> 3 & 7, OP_code & 7, 6); break;
  2976.       case 0x0F << 5 | 7: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 1, 0, 1, OP_code >> 3 & 7, OP_code & 7, 7); break;
  2977.       case 0x0F << 5 | 8: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 1, 0, 1, OP_code >> 3 & 7, OP_code & 7, 8); break;
  2978.       case 0x0F << 5 | 9: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 1, 0, 1, OP_code >> 3 & 7, OP_code & 7, 9); break;
  2979.       case 0x0F << 5 |10: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 1, 0, 1, OP_code >> 3 & 7, OP_code & 7, 10); break;
  2980.       case 0x0F << 5 |11: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 1, 0, 1, OP_code >> 3 & 7, OP_code & 7, 11); break;
  2981.       case 0x0F << 5 |12: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 1, 0, 1, OP_code >> 3 & 7, OP_code & 7, 12); break;
  2982.       case 0x0F << 5 |13: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 1, 0, 1, OP_code >> 3 & 7, OP_code & 7, 13); break;
  2983.       case 0x0F << 5 |14: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 1, 0, 1, OP_code >> 3 & 7, OP_code & 7, 14); break;
  2984.       case 0x0F << 5 |15: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 1, 0, 1, OP_code >> 3 & 7, OP_code & 7, 15); break;
  2985.       case 0x0F << 5 |16: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 1, 0, 1, OP_code >> 3 & 7, OP_code & 7, 16); break;
  2986.       case 0x0F << 5 |17: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 1, 0, 1, OP_code >> 3 & 7, OP_code & 7, 17); break;
  2987.       case 0x0F << 5 |18: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 1, 0, 1, OP_code >> 3 & 7, OP_code & 7, 18); break;
  2988.       case 0x0F << 5 |19: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 1, 0, 1, OP_code >> 3 & 7, OP_code & 7, 19); break;
  2989.       case 0x0F << 5 |20: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 1, 0, 1, OP_code >> 3 & 7, OP_code & 7, 20); break;
  2990.       case 0x0F << 5 |21: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 1, 0, 1, OP_code >> 3 & 7, OP_code & 7, 21); break;
  2991.       case 0x0F << 5 |22: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 1, 0, 1, OP_code >> 3 & 7, OP_code & 7, 22); break;
  2992.       case 0x0F << 5 |23: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 1, 0, 1, OP_code >> 3 & 7, OP_code & 7, 23); break;
  2993.       case 0x0F << 5 |24: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 1, 0, 1, OP_code >> 3 & 7, OP_code & 7, 24); break;
  2994.       case 0x0F << 5 |25: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 1, 0, 1, OP_code >> 3 & 7, OP_code & 7, 25); break;
  2995.       case 0x0F << 5 |26: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 1, 0, 1, OP_code >> 3 & 7, OP_code & 7, 26); break;
  2996.       case 0x0F << 5 |27: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 1, 0, 1, OP_code >> 3 & 7, OP_code & 7, 27); break;
  2997.       case 0x0F << 5 |28: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 1, 0, 1, OP_code >> 3 & 7, OP_code & 7, 28); break;
  2998.       case 0x0F << 5 |29: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 1, 0, 1, OP_code >> 3 & 7, OP_code & 7, 29); break;
  2999.       case 0x0F << 5 |30: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 1, 0, 1, OP_code >> 3 & 7, OP_code & 7, 30); break;
  3000.       case 0x0F << 5 |31: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 1, 0, 1, OP_code >> 3 & 7, OP_code & 7, 31); break;
  3001.  
  3002.       case 0x10 << 5 | 0: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 0, 0, 1, OP_code >> 3 & 7, OP_code & 7, 0 * 2); break;
  3003.       case 0x10 << 5 | 1: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 0, 0, 1, OP_code >> 3 & 7, OP_code & 7, 1 * 2); break;
  3004.       case 0x10 << 5 | 2: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 0, 0, 1, OP_code >> 3 & 7, OP_code & 7, 2 * 2); break;
  3005.       case 0x10 << 5 | 3: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 0, 0, 1, OP_code >> 3 & 7, OP_code & 7, 3 * 2); break;
  3006.       case 0x10 << 5 | 4: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 0, 0, 1, OP_code >> 3 & 7, OP_code & 7, 4 * 2); break;
  3007.       case 0x10 << 5 | 5: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 0, 0, 1, OP_code >> 3 & 7, OP_code & 7, 5 * 2); break;
  3008.       case 0x10 << 5 | 6: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 0, 0, 1, OP_code >> 3 & 7, OP_code & 7, 6 * 2); break;
  3009.       case 0x10 << 5 | 7: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 0, 0, 1, OP_code >> 3 & 7, OP_code & 7, 7 * 2); break;
  3010.       case 0x10 << 5 | 8: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 0, 0, 1, OP_code >> 3 & 7, OP_code & 7, 8 * 2); break;
  3011.       case 0x10 << 5 | 9: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 0, 0, 1, OP_code >> 3 & 7, OP_code & 7, 9 * 2); break;
  3012.       case 0x10 << 5 |10: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 0, 0, 1, OP_code >> 3 & 7, OP_code & 7, 10 * 2); break;
  3013.       case 0x10 << 5 |11: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 0, 0, 1, OP_code >> 3 & 7, OP_code & 7, 11 * 2); break;
  3014.       case 0x10 << 5 |12: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 0, 0, 1, OP_code >> 3 & 7, OP_code & 7, 12 * 2); break;
  3015.       case 0x10 << 5 |13: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 0, 0, 1, OP_code >> 3 & 7, OP_code & 7, 13 * 2); break;
  3016.       case 0x10 << 5 |14: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 0, 0, 1, OP_code >> 3 & 7, OP_code & 7, 14 * 2); break;
  3017.       case 0x10 << 5 |15: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 0, 0, 1, OP_code >> 3 & 7, OP_code & 7, 15 * 2); break;
  3018.       case 0x10 << 5 |16: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 0, 0, 1, OP_code >> 3 & 7, OP_code & 7, 16 * 2); break;
  3019.       case 0x10 << 5 |17: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 0, 0, 1, OP_code >> 3 & 7, OP_code & 7, 17 * 2); break;
  3020.       case 0x10 << 5 |18: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 0, 0, 1, OP_code >> 3 & 7, OP_code & 7, 18 * 2); break;
  3021.       case 0x10 << 5 |19: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 0, 0, 1, OP_code >> 3 & 7, OP_code & 7, 19 * 2); break;
  3022.       case 0x10 << 5 |20: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 0, 0, 1, OP_code >> 3 & 7, OP_code & 7, 20 * 2); break;
  3023.       case 0x10 << 5 |21: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 0, 0, 1, OP_code >> 3 & 7, OP_code & 7, 21 * 2); break;
  3024.       case 0x10 << 5 |22: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 0, 0, 1, OP_code >> 3 & 7, OP_code & 7, 22 * 2); break;
  3025.       case 0x10 << 5 |23: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 0, 0, 1, OP_code >> 3 & 7, OP_code & 7, 23 * 2); break;
  3026.       case 0x10 << 5 |24: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 0, 0, 1, OP_code >> 3 & 7, OP_code & 7, 24 * 2); break;
  3027.       case 0x10 << 5 |25: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 0, 0, 1, OP_code >> 3 & 7, OP_code & 7, 25 * 2); break;
  3028.       case 0x10 << 5 |26: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 0, 0, 1, OP_code >> 3 & 7, OP_code & 7, 26 * 2); break;
  3029.       case 0x10 << 5 |27: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 0, 0, 1, OP_code >> 3 & 7, OP_code & 7, 27 * 2); break;
  3030.       case 0x10 << 5 |28: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 0, 0, 1, OP_code >> 3 & 7, OP_code & 7, 28 * 2); break;
  3031.       case 0x10 << 5 |29: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 0, 0, 1, OP_code >> 3 & 7, OP_code & 7, 29 * 2); break;
  3032.       case 0x10 << 5 |30: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 0, 0, 1, OP_code >> 3 & 7, OP_code & 7, 30 * 2); break;
  3033.       case 0x10 << 5 |31: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 0, 0, 1, OP_code >> 3 & 7, OP_code & 7, 31 * 2); break;
  3034.  
  3035.       case 0x11 << 5 | 0: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 1, 0, 1, OP_code >> 3 & 7, OP_code & 7, 0 * 2); break;
  3036.       case 0x11 << 5 | 1: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 1, 0, 1, OP_code >> 3 & 7, OP_code & 7, 1 * 2); break;
  3037.       case 0x11 << 5 | 2: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 1, 0, 1, OP_code >> 3 & 7, OP_code & 7, 2 * 2); break;
  3038.       case 0x11 << 5 | 3: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 1, 0, 1, OP_code >> 3 & 7, OP_code & 7, 3 * 2); break;
  3039.       case 0x11 << 5 | 4: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 1, 0, 1, OP_code >> 3 & 7, OP_code & 7, 4 * 2); break;
  3040.       case 0x11 << 5 | 5: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 1, 0, 1, OP_code >> 3 & 7, OP_code & 7, 5 * 2); break;
  3041.       case 0x11 << 5 | 6: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 1, 0, 1, OP_code >> 3 & 7, OP_code & 7, 6 * 2); break;
  3042.       case 0x11 << 5 | 7: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 1, 0, 1, OP_code >> 3 & 7, OP_code & 7, 7 * 2); break;
  3043.       case 0x11 << 5 | 8: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 1, 0, 1, OP_code >> 3 & 7, OP_code & 7, 8 * 2); break;
  3044.       case 0x11 << 5 | 9: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 1, 0, 1, OP_code >> 3 & 7, OP_code & 7, 9 * 2); break;
  3045.       case 0x11 << 5 |10: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 1, 0, 1, OP_code >> 3 & 7, OP_code & 7, 10 * 2); break;
  3046.       case 0x11 << 5 |11: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 1, 0, 1, OP_code >> 3 & 7, OP_code & 7, 11 * 2); break;
  3047.       case 0x11 << 5 |12: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 1, 0, 1, OP_code >> 3 & 7, OP_code & 7, 12 * 2); break;
  3048.       case 0x11 << 5 |13: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 1, 0, 1, OP_code >> 3 & 7, OP_code & 7, 13 * 2); break;
  3049.       case 0x11 << 5 |14: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 1, 0, 1, OP_code >> 3 & 7, OP_code & 7, 14 * 2); break;
  3050.       case 0x11 << 5 |15: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 1, 0, 1, OP_code >> 3 & 7, OP_code & 7, 15 * 2); break;
  3051.       case 0x11 << 5 |16: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 1, 0, 1, OP_code >> 3 & 7, OP_code & 7, 16 * 2); break;
  3052.       case 0x11 << 5 |17: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 1, 0, 1, OP_code >> 3 & 7, OP_code & 7, 17 * 2); break;
  3053.       case 0x11 << 5 |18: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 1, 0, 1, OP_code >> 3 & 7, OP_code & 7, 18 * 2); break;
  3054.       case 0x11 << 5 |19: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 1, 0, 1, OP_code >> 3 & 7, OP_code & 7, 19 * 2); break;
  3055.       case 0x11 << 5 |20: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 1, 0, 1, OP_code >> 3 & 7, OP_code & 7, 20 * 2); break;
  3056.       case 0x11 << 5 |21: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 1, 0, 1, OP_code >> 3 & 7, OP_code & 7, 21 * 2); break;
  3057.       case 0x11 << 5 |22: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 1, 0, 1, OP_code >> 3 & 7, OP_code & 7, 22 * 2); break;
  3058.       case 0x11 << 5 |23: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 1, 0, 1, OP_code >> 3 & 7, OP_code & 7, 23 * 2); break;
  3059.       case 0x11 << 5 |24: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 1, 0, 1, OP_code >> 3 & 7, OP_code & 7, 24 * 2); break;
  3060.       case 0x11 << 5 |25: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 1, 0, 1, OP_code >> 3 & 7, OP_code & 7, 25 * 2); break;
  3061.       case 0x11 << 5 |26: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 1, 0, 1, OP_code >> 3 & 7, OP_code & 7, 26 * 2); break;
  3062.       case 0x11 << 5 |27: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 1, 0, 1, OP_code >> 3 & 7, OP_code & 7, 27 * 2); break;
  3063.       case 0x11 << 5 |28: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 1, 0, 1, OP_code >> 3 & 7, OP_code & 7, 28 * 2); break;
  3064.       case 0x11 << 5 |29: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 1, 0, 1, OP_code >> 3 & 7, OP_code & 7, 29 * 2); break;
  3065.       case 0x11 << 5 |30: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 1, 0, 1, OP_code >> 3 & 7, OP_code & 7, 30 * 2); break;
  3066.       case 0x11 << 5 |31: consume += isa_arm7_memory_access_sbh_base (agb, 1, 1, 0, 1, 0, 1, OP_code >> 3 & 7, OP_code & 7, 31 * 2); break;
  3067.  
  3068.       case 0x12 << 5 | 0: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 0, 13, 0 >> 2, (OP_code & 0xFF) * 4); break;
  3069.       case 0x12 << 5 | 1: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 0, 13, 1 >> 2, (OP_code & 0xFF) * 4); break;
  3070.       case 0x12 << 5 | 2: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 0, 13, 2 >> 2, (OP_code & 0xFF) * 4); break;
  3071.       case 0x12 << 5 | 3: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 0, 13, 3 >> 2, (OP_code & 0xFF) * 4); break;
  3072.       case 0x12 << 5 | 4: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 0, 13, 4 >> 2, (OP_code & 0xFF) * 4); break;
  3073.       case 0x12 << 5 | 5: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 0, 13, 5 >> 2, (OP_code & 0xFF) * 4); break;
  3074.       case 0x12 << 5 | 6: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 0, 13, 6 >> 2, (OP_code & 0xFF) * 4); break;
  3075.       case 0x12 << 5 | 7: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 0, 13, 7 >> 2, (OP_code & 0xFF) * 4); break;
  3076.       case 0x12 << 5 | 8: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 0, 13, 8 >> 2, (OP_code & 0xFF) * 4); break;
  3077.       case 0x12 << 5 | 9: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 0, 13, 9 >> 2, (OP_code & 0xFF) * 4); break;
  3078.       case 0x12 << 5 |10: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 0, 13, 10 >> 2, (OP_code & 0xFF) * 4); break;
  3079.       case 0x12 << 5 |11: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 0, 13, 11 >> 2, (OP_code & 0xFF) * 4); break;
  3080.       case 0x12 << 5 |12: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 0, 13, 12 >> 2, (OP_code & 0xFF) * 4); break;
  3081.       case 0x12 << 5 |13: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 0, 13, 13 >> 2, (OP_code & 0xFF) * 4); break;
  3082.       case 0x12 << 5 |14: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 0, 13, 14 >> 2, (OP_code & 0xFF) * 4); break;
  3083.       case 0x12 << 5 |15: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 0, 13, 15 >> 2, (OP_code & 0xFF) * 4); break;
  3084.       case 0x12 << 5 |16: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 0, 13, 16 >> 2, (OP_code & 0xFF) * 4); break;
  3085.       case 0x12 << 5 |17: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 0, 13, 17 >> 2, (OP_code & 0xFF) * 4); break;
  3086.       case 0x12 << 5 |18: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 0, 13, 18 >> 2, (OP_code & 0xFF) * 4); break;
  3087.       case 0x12 << 5 |19: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 0, 13, 19 >> 2, (OP_code & 0xFF) * 4); break;
  3088.       case 0x12 << 5 |20: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 0, 13, 20 >> 2, (OP_code & 0xFF) * 4); break;
  3089.       case 0x12 << 5 |21: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 0, 13, 21 >> 2, (OP_code & 0xFF) * 4); break;
  3090.       case 0x12 << 5 |22: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 0, 13, 22 >> 2, (OP_code & 0xFF) * 4); break;
  3091.       case 0x12 << 5 |23: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 0, 13, 23 >> 2, (OP_code & 0xFF) * 4); break;
  3092.       case 0x12 << 5 |24: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 0, 13, 24 >> 2, (OP_code & 0xFF) * 4); break;
  3093.       case 0x12 << 5 |25: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 0, 13, 25 >> 2, (OP_code & 0xFF) * 4); break;
  3094.       case 0x12 << 5 |26: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 0, 13, 26 >> 2, (OP_code & 0xFF) * 4); break;
  3095.       case 0x12 << 5 |27: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 0, 13, 27 >> 2, (OP_code & 0xFF) * 4); break;
  3096.       case 0x12 << 5 |28: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 0, 13, 28 >> 2, (OP_code & 0xFF) * 4); break;
  3097.       case 0x12 << 5 |29: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 0, 13, 29 >> 2, (OP_code & 0xFF) * 4); break;
  3098.       case 0x12 << 5 |30: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 0, 13, 30 >> 2, (OP_code & 0xFF) * 4); break;
  3099.       case 0x12 << 5 |31: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 0, 13, 31 >> 2, (OP_code & 0xFF) * 4); break;
  3100.  
  3101.       case 0x13 << 5 | 0: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 1, 13, 0 >> 2, (OP_code & 0xFF) * 4); break;
  3102.       case 0x13 << 5 | 1: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 1, 13, 1 >> 2, (OP_code & 0xFF) * 4); break;
  3103.       case 0x13 << 5 | 2: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 1, 13, 2 >> 2, (OP_code & 0xFF) * 4); break;
  3104.       case 0x13 << 5 | 3: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 1, 13, 3 >> 2, (OP_code & 0xFF) * 4); break;
  3105.       case 0x13 << 5 | 4: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 1, 13, 4 >> 2, (OP_code & 0xFF) * 4); break;
  3106.       case 0x13 << 5 | 5: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 1, 13, 5 >> 2, (OP_code & 0xFF) * 4); break;
  3107.       case 0x13 << 5 | 6: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 1, 13, 6 >> 2, (OP_code & 0xFF) * 4); break;
  3108.       case 0x13 << 5 | 7: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 1, 13, 7 >> 2, (OP_code & 0xFF) * 4); break;
  3109.       case 0x13 << 5 | 8: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 1, 13, 8 >> 2, (OP_code & 0xFF) * 4); break;
  3110.       case 0x13 << 5 | 9: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 1, 13, 9 >> 2, (OP_code & 0xFF) * 4); break;
  3111.       case 0x13 << 5 |10: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 1, 13, 10 >> 2, (OP_code & 0xFF) * 4); break;
  3112.       case 0x13 << 5 |11: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 1, 13, 11 >> 2, (OP_code & 0xFF) * 4); break;
  3113.       case 0x13 << 5 |12: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 1, 13, 12 >> 2, (OP_code & 0xFF) * 4); break;
  3114.       case 0x13 << 5 |13: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 1, 13, 13 >> 2, (OP_code & 0xFF) * 4); break;
  3115.       case 0x13 << 5 |14: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 1, 13, 14 >> 2, (OP_code & 0xFF) * 4); break;
  3116.       case 0x13 << 5 |15: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 1, 13, 15 >> 2, (OP_code & 0xFF) * 4); break;
  3117.       case 0x13 << 5 |16: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 1, 13, 16 >> 2, (OP_code & 0xFF) * 4); break;
  3118.       case 0x13 << 5 |17: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 1, 13, 17 >> 2, (OP_code & 0xFF) * 4); break;
  3119.       case 0x13 << 5 |18: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 1, 13, 18 >> 2, (OP_code & 0xFF) * 4); break;
  3120.       case 0x13 << 5 |19: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 1, 13, 19 >> 2, (OP_code & 0xFF) * 4); break;
  3121.       case 0x13 << 5 |20: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 1, 13, 20 >> 2, (OP_code & 0xFF) * 4); break;
  3122.       case 0x13 << 5 |21: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 1, 13, 21 >> 2, (OP_code & 0xFF) * 4); break;
  3123.       case 0x13 << 5 |22: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 1, 13, 22 >> 2, (OP_code & 0xFF) * 4); break;
  3124.       case 0x13 << 5 |23: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 1, 13, 23 >> 2, (OP_code & 0xFF) * 4); break;
  3125.       case 0x13 << 5 |24: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 1, 13, 24 >> 2, (OP_code & 0xFF) * 4); break;
  3126.       case 0x13 << 5 |25: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 1, 13, 25 >> 2, (OP_code & 0xFF) * 4); break;
  3127.       case 0x13 << 5 |26: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 1, 13, 26 >> 2, (OP_code & 0xFF) * 4); break;
  3128.       case 0x13 << 5 |27: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 1, 13, 27 >> 2, (OP_code & 0xFF) * 4); break;
  3129.       case 0x13 << 5 |28: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 1, 13, 28 >> 2, (OP_code & 0xFF) * 4); break;
  3130.       case 0x13 << 5 |29: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 1, 13, 29 >> 2, (OP_code & 0xFF) * 4); break;
  3131.       case 0x13 << 5 |30: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 1, 13, 30 >> 2, (OP_code & 0xFF) * 4); break;
  3132.       case 0x13 << 5 |31: consume += isa_arm7_memory_access_ubw_base (agb, 1, 1, 0, 0, 1, 13, 31 >> 2, (OP_code & 0xFF) * 4); break;
  3133.  
  3134.       case 0x14 << 5 | 0: regs[0 >> 2] = (regs[15] & ARM7_CODE_MASK) + (OP_code & 0xFF) * 4; consume ++; break;
  3135.       case 0x14 << 5 | 1: regs[1 >> 2] = (regs[15] & ARM7_CODE_MASK) + (OP_code & 0xFF) * 4; consume ++; break;
  3136.       case 0x14 << 5 | 2: regs[2 >> 2] = (regs[15] & ARM7_CODE_MASK) + (OP_code & 0xFF) * 4; consume ++; break;
  3137.       case 0x14 << 5 | 3: regs[3 >> 2] = (regs[15] & ARM7_CODE_MASK) + (OP_code & 0xFF) * 4; consume ++; break;
  3138.       case 0x14 << 5 | 4: regs[4 >> 2] = (regs[15] & ARM7_CODE_MASK) + (OP_code & 0xFF) * 4; consume ++; break;
  3139.       case 0x14 << 5 | 5: regs[5 >> 2] = (regs[15] & ARM7_CODE_MASK) + (OP_code & 0xFF) * 4; consume ++; break;
  3140.       case 0x14 << 5 | 6: regs[6 >> 2] = (regs[15] & ARM7_CODE_MASK) + (OP_code & 0xFF) * 4; consume ++; break;
  3141.       case 0x14 << 5 | 7: regs[7 >> 2] = (regs[15] & ARM7_CODE_MASK) + (OP_code & 0xFF) * 4; consume ++; break;
  3142.       case 0x14 << 5 | 8: regs[8 >> 2] = (regs[15] & ARM7_CODE_MASK) + (OP_code & 0xFF) * 4; consume ++; break;
  3143.       case 0x14 << 5 | 9: regs[9 >> 2] = (regs[15] & ARM7_CODE_MASK) + (OP_code & 0xFF) * 4; consume ++; break;
  3144.       case 0x14 << 5 |10: regs[10 >> 2] = (regs[15] & ARM7_CODE_MASK) + (OP_code & 0xFF) * 4; consume ++; break;
  3145.       case 0x14 << 5 |11: regs[11 >> 2] = (regs[15] & ARM7_CODE_MASK) + (OP_code & 0xFF) * 4; consume ++; break;
  3146.       case 0x14 << 5 |12: regs[12 >> 2] = (regs[15] & ARM7_CODE_MASK) + (OP_code & 0xFF) * 4; consume ++; break;
  3147.       case 0x14 << 5 |13: regs[13 >> 2] = (regs[15] & ARM7_CODE_MASK) + (OP_code & 0xFF) * 4; consume ++; break;
  3148.       case 0x14 << 5 |14: regs[14 >> 2] = (regs[15] & ARM7_CODE_MASK) + (OP_code & 0xFF) * 4; consume ++; break;
  3149.       case 0x14 << 5 |15: regs[15 >> 2] = (regs[15] & ARM7_CODE_MASK) + (OP_code & 0xFF) * 4; consume ++; break;
  3150.       case 0x14 << 5 |16: regs[16 >> 2] = (regs[15] & ARM7_CODE_MASK) + (OP_code & 0xFF) * 4; consume ++; break;
  3151.       case 0x14 << 5 |17: regs[17 >> 2] = (regs[15] & ARM7_CODE_MASK) + (OP_code & 0xFF) * 4; consume ++; break;
  3152.       case 0x14 << 5 |18: regs[18 >> 2] = (regs[15] & ARM7_CODE_MASK) + (OP_code & 0xFF) * 4; consume ++; break;
  3153.       case 0x14 << 5 |19: regs[19 >> 2] = (regs[15] & ARM7_CODE_MASK) + (OP_code & 0xFF) * 4; consume ++; break;
  3154.       case 0x14 << 5 |20: regs[20 >> 2] = (regs[15] & ARM7_CODE_MASK) + (OP_code & 0xFF) * 4; consume ++; break;
  3155.       case 0x14 << 5 |21: regs[21 >> 2] = (regs[15] & ARM7_CODE_MASK) + (OP_code & 0xFF) * 4; consume ++; break;
  3156.       case 0x14 << 5 |22: regs[22 >> 2] = (regs[15] & ARM7_CODE_MASK) + (OP_code & 0xFF) * 4; consume ++; break;
  3157.       case 0x14 << 5 |23: regs[23 >> 2] = (regs[15] & ARM7_CODE_MASK) + (OP_code & 0xFF) * 4; consume ++; break;
  3158.       case 0x14 << 5 |24: regs[24 >> 2] = (regs[15] & ARM7_CODE_MASK) + (OP_code & 0xFF) * 4; consume ++; break;
  3159.       case 0x14 << 5 |25: regs[25 >> 2] = (regs[15] & ARM7_CODE_MASK) + (OP_code & 0xFF) * 4; consume ++; break;
  3160.       case 0x14 << 5 |26: regs[26 >> 2] = (regs[15] & ARM7_CODE_MASK) + (OP_code & 0xFF) * 4; consume ++; break;
  3161.       case 0x14 << 5 |27: regs[27 >> 2] = (regs[15] & ARM7_CODE_MASK) + (OP_code & 0xFF) * 4; consume ++; break;
  3162.       case 0x14 << 5 |28: regs[28 >> 2] = (regs[15] & ARM7_CODE_MASK) + (OP_code & 0xFF) * 4; consume ++; break;
  3163.       case 0x14 << 5 |29: regs[29 >> 2] = (regs[15] & ARM7_CODE_MASK) + (OP_code & 0xFF) * 4; consume ++; break;
  3164.       case 0x14 << 5 |30: regs[30 >> 2] = (regs[15] & ARM7_CODE_MASK) + (OP_code & 0xFF) * 4; consume ++; break;
  3165.       case 0x14 << 5 |31: regs[31 >> 2] = (regs[15] & ARM7_CODE_MASK) + (OP_code & 0xFF) * 4; consume ++; break;
  3166.  
  3167.       case 0x15 << 5 | 0: regs[0 >> 2] = regs[13] + (OP_code & 0xFF) * 4; consume ++; break;
  3168.       case 0x15 << 5 | 1: regs[1 >> 2] = regs[13] + (OP_code & 0xFF) * 4; consume ++; break;
  3169.       case 0x15 << 5 | 2: regs[2 >> 2] = regs[13] + (OP_code & 0xFF) * 4; consume ++; break;
  3170.       case 0x15 << 5 | 3: regs[3 >> 2] = regs[13] + (OP_code & 0xFF) * 4; consume ++; break;
  3171.       case 0x15 << 5 | 4: regs[4 >> 2] = regs[13] + (OP_code & 0xFF) * 4; consume ++; break;
  3172.       case 0x15 << 5 | 5: regs[5 >> 2] = regs[13] + (OP_code & 0xFF) * 4; consume ++; break;
  3173.       case 0x15 << 5 | 6: regs[6 >> 2] = regs[13] + (OP_code & 0xFF) * 4; consume ++; break;
  3174.       case 0x15 << 5 | 7: regs[7 >> 2] = regs[13] + (OP_code & 0xFF) * 4; consume ++; break;
  3175.       case 0x15 << 5 | 8: regs[8 >> 2] = regs[13] + (OP_code & 0xFF) * 4; consume ++; break;
  3176.       case 0x15 << 5 | 9: regs[9 >> 2] = regs[13] + (OP_code & 0xFF) * 4; consume ++; break;
  3177.       case 0x15 << 5 |10: regs[10 >> 2] = regs[13] + (OP_code & 0xFF) * 4; consume ++; break;
  3178.       case 0x15 << 5 |11: regs[11 >> 2] = regs[13] + (OP_code & 0xFF) * 4; consume ++; break;
  3179.       case 0x15 << 5 |12: regs[12 >> 2] = regs[13] + (OP_code & 0xFF) * 4; consume ++; break;
  3180.       case 0x15 << 5 |13: regs[13 >> 2] = regs[13] + (OP_code & 0xFF) * 4; consume ++; break;
  3181.       case 0x15 << 5 |14: regs[14 >> 2] = regs[13] + (OP_code & 0xFF) * 4; consume ++; break;
  3182.       case 0x15 << 5 |15: regs[15 >> 2] = regs[13] + (OP_code & 0xFF) * 4; consume ++; break;
  3183.       case 0x15 << 5 |16: regs[16 >> 2] = regs[13] + (OP_code & 0xFF) * 4; consume ++; break;
  3184.       case 0x15 << 5 |17: regs[17 >> 2] = regs[13] + (OP_code & 0xFF) * 4; consume ++; break;
  3185.       case 0x15 << 5 |18: regs[18 >> 2] = regs[13] + (OP_code & 0xFF) * 4; consume ++; break;
  3186.       case 0x15 << 5 |19: regs[19 >> 2] = regs[13] + (OP_code & 0xFF) * 4; consume ++; break;
  3187.       case 0x15 << 5 |20: regs[20 >> 2] = regs[13] + (OP_code & 0xFF) * 4; consume ++; break;
  3188.       case 0x15 << 5 |21: regs[21 >> 2] = regs[13] + (OP_code & 0xFF) * 4; consume ++; break;
  3189.       case 0x15 << 5 |22: regs[22 >> 2] = regs[13] + (OP_code & 0xFF) * 4; consume ++; break;
  3190.       case 0x15 << 5 |23: regs[23 >> 2] = regs[13] + (OP_code & 0xFF) * 4; consume ++; break;
  3191.       case 0x15 << 5 |24: regs[24 >> 2] = regs[13] + (OP_code & 0xFF) * 4; consume ++; break;
  3192.       case 0x15 << 5 |25: regs[25 >> 2] = regs[13] + (OP_code & 0xFF) * 4; consume ++; break;
  3193.       case 0x15 << 5 |26: regs[26 >> 2] = regs[13] + (OP_code & 0xFF) * 4; consume ++; break;
  3194.       case 0x15 << 5 |27: regs[27 >> 2] = regs[13] + (OP_code & 0xFF) * 4; consume ++; break;
  3195.       case 0x15 << 5 |28: regs[28 >> 2] = regs[13] + (OP_code & 0xFF) * 4; consume ++; break;
  3196.       case 0x15 << 5 |29: regs[29 >> 2] = regs[13] + (OP_code & 0xFF) * 4; consume ++; break;
  3197.       case 0x15 << 5 |30: regs[30 >> 2] = regs[13] + (OP_code & 0xFF) * 4; consume ++; break;
  3198.       case 0x15 << 5 |31: regs[31 >> 2] = regs[13] + (OP_code & 0xFF) * 4; consume ++; break;
  3199.  
  3200. #define THUMB_COND_CASE(cond_code) \
  3201.         case 0xD << 6 | (cond_code) << 2 | 0:\
  3202.         case 0xD << 6 | (cond_code) << 2 | 1:\
  3203.         case 0xD << 6 | (cond_code) << 2 | 2:\
  3204.         case 0xD << 6 | (cond_code) << 2 | 3
  3205.  
  3206. #define THUMB_JCC { const int8_t offset = OP_code & 0xFF; const int32_t offset32 = offset; regs[15] += offset32 * 2;  consume += thumb_flush (agb) + 2; break; }
  3207.  
  3208.         THUMB_COND_CASE (0x00): if (arm->cpsr.z != 0) THUMB_JCC regs[15] += 2; return consume + 1;
  3209.         THUMB_COND_CASE (0x01): if (arm->cpsr.z == 0) THUMB_JCC regs[15] += 2; return consume + 1;
  3210.         THUMB_COND_CASE (0x02): if (arm->cpsr.c != 0) THUMB_JCC regs[15] += 2; return consume + 1;
  3211.         THUMB_COND_CASE (0x03): if (arm->cpsr.c == 0) THUMB_JCC regs[15] += 2; return consume + 1;
  3212.         THUMB_COND_CASE (0x04): if (arm->cpsr.n != 0) THUMB_JCC regs[15] += 2; return consume + 1;
  3213.         THUMB_COND_CASE (0x05): if (arm->cpsr.n == 0) THUMB_JCC regs[15] += 2; return consume + 1;
  3214.         THUMB_COND_CASE (0x06): if (arm->cpsr.v != 0) THUMB_JCC regs[15] += 2; return consume + 1;
  3215.         THUMB_COND_CASE (0x07): if (arm->cpsr.v == 0) THUMB_JCC regs[15] += 2; return consume + 1;
  3216.         THUMB_COND_CASE (0x08): if (arm->cpsr.c != 0 && arm->cpsr.z == 0) THUMB_JCC regs[15] += 2; return consume + 1;
  3217.         THUMB_COND_CASE (0x09): if (arm->cpsr.c == 0 || arm->cpsr.z != 0) THUMB_JCC regs[15] += 2; return consume + 1;
  3218.         THUMB_COND_CASE (0x0A): if (arm->cpsr.n == arm->cpsr.v) THUMB_JCC regs[15] += 2; return consume + 1;
  3219.         THUMB_COND_CASE (0x0B): if (arm->cpsr.n != arm->cpsr.v) THUMB_JCC regs[15] += 2; return consume + 1;
  3220.         THUMB_COND_CASE (0x0C): if (arm->cpsr.z == 0 && (arm->cpsr.n == arm->cpsr.v)) THUMB_JCC regs[15] += 2; return consume + 1;
  3221.         THUMB_COND_CASE (0x0D): if (arm->cpsr.z != 0 || (arm->cpsr.n != arm->cpsr.v)) THUMB_JCC regs[15] += 2; return consume + 1;
  3222.         THUMB_COND_CASE (0x0E): THUMB_JCC
  3223.         default:
  3224.           assert (0);
  3225.           break;
  3226.       }
  3227.       regs[15] += 2;
  3228.     } else {
  3229.       struct arm7_ldr_sbh_throat {
  3230.         uint32_t _1:1;
  3231.         uint32_t h:1;
  3232.         uint32_t s:1;
  3233.         uint32_t __1:1;
  3234.         uint32_t l:1;
  3235.         uint32_t w:1;
  3236.         uint32_t x:1; /* LDR SBH reg | LDR SBH imm */
  3237.         uint32_t u:1;
  3238.         uint32_t p:1;
  3239.         uint32_t align:23;
  3240.       };
  3241.  
  3242.       struct arm7_ldr_ubw_throat {
  3243.         uint32_t l:1;
  3244.         uint32_t w:1;
  3245.         uint32_t b:1;
  3246.         uint32_t u:1;
  3247.         uint32_t p:1;
  3248.         uint32_t i:1;
  3249.         uint32_t align:26;
  3250.       };
  3251.  
  3252.       struct arm7_ldm_throat {
  3253.         uint32_t l:1;
  3254.         uint32_t w:1;
  3255.         uint32_t s:1;
  3256.         uint32_t u:1;
  3257.         uint32_t p:1;
  3258.         uint32_t align:27;
  3259.       };
  3260.       const uint32_t OP_code = arm->opcode[0];
  3261.       const uint32_t OP_throat = OP_code >> 16 & 0xFF0 | OP_code >> 4 & 0xF;
  3262.       const uint32_t OP_cond = OP_code & LSHIFT_RANGE_MASK (0x0F, 28);
  3263.       const uint32_t pc = regs[15] - 8;
  3264.       arm->opcode[0] = arm->opcode[1];
  3265.       consume +=  arm7_fecth_n (agb, regs[15], & arm->opcode[1]);
  3266.      
  3267.    //   if (pc == 0xa0)
  3268.      // __asm int 3
  3269.  
  3270.  
  3271.       //if (old_pc != pc)
  3272.       //  printf ("pc:arm r12:%d-> %07X\n", regs[12], pc);
  3273.       old_r1 = regs[1];
  3274.       old_r10 = regs[10];
  3275.       old_pc = pc;
  3276.      // if (old_r1 == 0x6000000
  3277.       //  && old_pc == 0xC08)
  3278.       //  __asm int 3
  3279.       /* check arm7 cond field */
  3280.       switch (OP_cond) {
  3281.       case LSHIFT_RANGE_MASK (0x00, 28): if (arm->cpsr.z != 0) break; regs[15] += 4; return consume + 1;
  3282.       case LSHIFT_RANGE_MASK (0x01, 28): if (arm->cpsr.z == 0) break; regs[15] += 4; return consume + 1;
  3283.       case LSHIFT_RANGE_MASK (0x02, 28): if (arm->cpsr.c != 0) break; regs[15] += 4; return consume + 1;
  3284.       case LSHIFT_RANGE_MASK (0x03, 28): if (arm->cpsr.c == 0) break; regs[15] += 4; return consume + 1;
  3285.       case LSHIFT_RANGE_MASK (0x04, 28): if (arm->cpsr.n != 0) break; regs[15] += 4; return consume + 1;
  3286.       case LSHIFT_RANGE_MASK (0x05, 28): if (arm->cpsr.n == 0) break; regs[15] += 4; return consume + 1;
  3287.       case LSHIFT_RANGE_MASK (0x06, 28): if (arm->cpsr.v != 0) break; regs[15] += 4; return consume + 1;
  3288.       case LSHIFT_RANGE_MASK (0x07, 28): if (arm->cpsr.v == 0) break; regs[15] += 4; return consume + 1;
  3289.       case LSHIFT_RANGE_MASK (0x08, 28): if (arm->cpsr.c != 0 && arm->cpsr.z == 0) break; regs[15] += 4; return consume + 1;
  3290.       case LSHIFT_RANGE_MASK (0x09, 28): if (arm->cpsr.c == 0 || arm->cpsr.z != 0) break; regs[15] += 4; return consume + 1;
  3291.       case LSHIFT_RANGE_MASK (0x0A, 28): if (arm->cpsr.n == arm->cpsr.v) break; regs[15] += 4; return consume + 1;
  3292.       case LSHIFT_RANGE_MASK (0x0B, 28): if (arm->cpsr.n != arm->cpsr.v) break; regs[15] += 4; return consume + 1;
  3293.       case LSHIFT_RANGE_MASK (0x0C, 28): if (arm->cpsr.z == 0 && (arm->cpsr.n == arm->cpsr.v)) break; regs[15] += 4; return consume + 1;
  3294.       case LSHIFT_RANGE_MASK (0x0D, 28): if (arm->cpsr.z != 0 || (arm->cpsr.n != arm->cpsr.v)) break; regs[15] += 4; return consume + 1;
  3295.       case LSHIFT_RANGE_MASK (0x0E, 28): break;
  3296.       case LSHIFT_RANGE_MASK (0x0F, 28):  regs[15] += 4; return consume + 1;
  3297.       default: assert (0); break;
  3298.       }
  3299.       /* arm7 opcode decode *.*/
  3300.       switch (OP_throat) {
  3301.       case 0x009: consume += isa_arm7_mul (agb, OP_code, 0, 0); break;
  3302.       case 0x019: consume += isa_arm7_mul (agb, OP_code, 0, 1); break;
  3303.       case 0x029: consume += isa_arm7_mul (agb, OP_code, 1, 0); break;
  3304.       case 0x039: consume += isa_arm7_mul (agb, OP_code, 1, 1); break;
  3305.  
  3306.       case 0x089: consume += isa_arm7_mul_long (agb, OP_code, 0, 0, 0); break;
  3307.       case 0x099: consume += isa_arm7_mul_long (agb, OP_code, 0, 0, 1); break;
  3308.       case 0x0A9: consume += isa_arm7_mul_long (agb, OP_code, 0, 1, 0); break;
  3309.       case 0x0B9: consume += isa_arm7_mul_long (agb, OP_code, 0, 1, 1); break;
  3310.       case 0x0C9: consume += isa_arm7_mul_long (agb, OP_code, 1, 0, 0); break;
  3311.       case 0x0D9: consume += isa_arm7_mul_long (agb, OP_code, 1, 0, 1); break;
  3312.       case 0x0E9: consume += isa_arm7_mul_long (agb, OP_code, 1, 1, 0); break;
  3313.       case 0x0F9: consume += isa_arm7_mul_long (agb, OP_code, 1, 1, 1); break;
  3314.  
  3315.       case 0x109: consume += isa_arm7_atomic_swap (agb, OP_code, 0); break;
  3316.       case 0x149: consume += isa_arm7_atomic_swap (agb, OP_code, 1); break;
  3317.       case 0x100: consume += isa_arm7_psr_load (agb, OP_code); break;
  3318.       case 0x140: consume += isa_arm7_psr_load (agb, OP_code); break;
  3319.  
  3320.       case 0x320: consume += isa_arm7_psr_store_imm (agb, OP_code); break;
  3321.       case 0x321: consume += isa_arm7_psr_store_imm (agb, OP_code); break;
  3322.       case 0x322: consume += isa_arm7_psr_store_imm (agb, OP_code); break;
  3323.       case 0x323: consume += isa_arm7_psr_store_imm (agb, OP_code); break;
  3324.       case 0x324: consume += isa_arm7_psr_store_imm (agb, OP_code); break;
  3325.       case 0x325: consume += isa_arm7_psr_store_imm (agb, OP_code); break;
  3326.       case 0x326: consume += isa_arm7_psr_store_imm (agb, OP_code); break;
  3327.       case 0x327: consume += isa_arm7_psr_store_imm (agb, OP_code); break;
  3328.       case 0x328: consume += isa_arm7_psr_store_imm (agb, OP_code); break;
  3329.       case 0x329: consume += isa_arm7_psr_store_imm (agb, OP_code); break;
  3330.       case 0x32A: consume += isa_arm7_psr_store_imm (agb, OP_code); break;
  3331.       case 0x32B: consume += isa_arm7_psr_store_imm (agb, OP_code); break;
  3332.       case 0x32C: consume += isa_arm7_psr_store_imm (agb, OP_code); break;
  3333.       case 0x32D: consume += isa_arm7_psr_store_imm (agb, OP_code); break;
  3334.       case 0x32E: consume += isa_arm7_psr_store_imm (agb, OP_code); break;
  3335.       case 0x32F: consume += isa_arm7_psr_store_imm (agb, OP_code); break;
  3336.  
  3337.       case 0x360: consume += isa_arm7_psr_store_imm (agb, OP_code); break;
  3338.       case 0x361: consume += isa_arm7_psr_store_imm (agb, OP_code); break;
  3339.       case 0x362: consume += isa_arm7_psr_store_imm (agb, OP_code); break;
  3340.       case 0x363: consume += isa_arm7_psr_store_imm (agb, OP_code); break;
  3341.       case 0x364: consume += isa_arm7_psr_store_imm (agb, OP_code); break;
  3342.       case 0x365: consume += isa_arm7_psr_store_imm (agb, OP_code); break;
  3343.       case 0x366: consume += isa_arm7_psr_store_imm (agb, OP_code); break;
  3344.       case 0x367: consume += isa_arm7_psr_store_imm (agb, OP_code); break;
  3345.       case 0x368: consume += isa_arm7_psr_store_imm (agb, OP_code); break;
  3346.       case 0x369: consume += isa_arm7_psr_store_imm (agb, OP_code); break;
  3347.       case 0x36A: consume += isa_arm7_psr_store_imm (agb, OP_code); break;
  3348.       case 0x36B: consume += isa_arm7_psr_store_imm (agb, OP_code); break;
  3349.       case 0x36C: consume += isa_arm7_psr_store_imm (agb, OP_code); break;
  3350.       case 0x36D: consume += isa_arm7_psr_store_imm (agb, OP_code); break;
  3351.       case 0x36E: consume += isa_arm7_psr_store_imm (agb, OP_code); break;
  3352.       case 0x36F: consume += isa_arm7_psr_store_imm (agb, OP_code); break;
  3353.  
  3354.       case 0x120: consume += isa_arm7_psr_store_reg (agb, OP_code); break;
  3355.       case 0x160: consume += isa_arm7_psr_store_reg (agb, OP_code); break;
  3356.  
  3357.       case 0x121: consume += isa_arm7_branch_exchange (agb, OP_code); if (arm->cpsr.thumb != 0) regs[15] -= 2;   break;
  3358.  
  3359.       case 0xF00: case 0xF01: case 0xF02: case 0xF03:
  3360.       case 0xF04: case 0xF05: case 0xF06: case 0xF07:
  3361.       case 0xF08: case 0xF09: case 0xF0A: case 0xF0B:
  3362.       case 0xF0C: case 0xF0D: case 0xF0E:
  3363.       case 0xF0F:
  3364.       case 0xF10: case 0xF11: case 0xF12: case 0xF13:
  3365.       case 0xF14: case 0xF15: case 0xF16: case 0xF17:
  3366.       case 0xF18: case 0xF19: case 0xF1A: case 0xF1B:
  3367.       case 0xF1C: case 0xF1D: case 0xF1E:
  3368.       case 0xF1F:
  3369.       case 0xF20: case 0xF21: case 0xF22: case 0xF23:
  3370.       case 0xF24: case 0xF25: case 0xF26: case 0xF27:
  3371.       case 0xF28: case 0xF29: case 0xF2A: case 0xF2B:
  3372.       case 0xF2C: case 0xF2D: case 0xF2E:
  3373.       case 0xF2F:
  3374.       case 0xF30: case 0xF31: case 0xF32: case 0xF33:
  3375.       case 0xF34: case 0xF35: case 0xF36: case 0xF37:
  3376.       case 0xF38: case 0xF39: case 0xF3A: case 0xF3B:
  3377.       case 0xF3C: case 0xF3D: case 0xF3E:
  3378.       case 0xF3F:
  3379.       case 0xF40: case 0xF41: case 0xF42: case 0xF43:
  3380.       case 0xF44: case 0xF45: case 0xF46: case 0xF47:
  3381.       case 0xF48: case 0xF49: case 0xF4A: case 0xF4B:
  3382.       case 0xF4C: case 0xF4D: case 0xF4E:
  3383.       case 0xF4F:
  3384.       case 0xF50: case 0xF51: case 0xF52: case 0xF53:
  3385.       case 0xF54: case 0xF55: case 0xF56: case 0xF57:
  3386.       case 0xF58: case 0xF59: case 0xF5A: case 0xF5B:
  3387.       case 0xF5C: case 0xF5D: case 0xF5E:
  3388.       case 0xF5F:
  3389.       case 0xF60: case 0xF61: case 0xF62: case 0xF63:
  3390.       case 0xF64: case 0xF65: case 0xF66: case 0xF67:
  3391.       case 0xF68: case 0xF69: case 0xF6A: case 0xF6B:
  3392.       case 0xF6C: case 0xF6D: case 0xF6E:
  3393.       case 0xF6F:
  3394.       case 0xF70: case 0xF71: case 0xF72: case 0xF73:
  3395.       case 0xF74: case 0xF75: case 0xF76: case 0xF77:
  3396.       case 0xF78: case 0xF79: case 0xF7A: case 0xF7B:
  3397.       case 0xF7C: case 0xF7D: case 0xF7E:
  3398.       case 0xF7F:
  3399.       case 0xF80: case 0xF81: case 0xF82: case 0xF83:
  3400.       case 0xF84: case 0xF85: case 0xF86: case 0xF87:
  3401.       case 0xF88: case 0xF89: case 0xF8A: case 0xF8B:
  3402.       case 0xF8C: case 0xF8D: case 0xF8E:
  3403.       case 0xF8F:
  3404.       case 0xF90: case 0xF91: case 0xF92: case 0xF93:
  3405.       case 0xF94: case 0xF95: case 0xF96: case 0xF97:
  3406.       case 0xF98: case 0xF99: case 0xF9A: case 0xF9B:
  3407.       case 0xF9C: case 0xF9D: case 0xF9E:
  3408.       case 0xF9F:
  3409.       case 0xFA0: case 0xFA1: case 0xFA2: case 0xFA3:
  3410.       case 0xFA4: case 0xFA5: case 0xFA6: case 0xFA7:
  3411.       case 0xFA8: case 0xFA9: case 0xFAA: case 0xFAB:
  3412.       case 0xFAC: case 0xFAD: case 0xFAE:
  3413.       case 0xFAF:
  3414.       case 0xFB0: case 0xFB1: case 0xFB2: case 0xFB3:
  3415.       case 0xFB4: case 0xFB5: case 0xFB6: case 0xFB7:
  3416.       case 0xFB8: case 0xFB9: case 0xFBA: case 0xFBB:
  3417.       case 0xFBC: case 0xFBD: case 0xFBE:
  3418.       case 0xFBF:
  3419.       case 0xFC0: case 0xFC1: case 0xFC2: case 0xFC3:
  3420.       case 0xFC4: case 0xFC5: case 0xFC6: case 0xFC7:
  3421.       case 0xFC8: case 0xFC9: case 0xFCA: case 0xFCB:
  3422.       case 0xFCC: case 0xFCD: case 0xFCE:
  3423.       case 0xFCF:
  3424.       case 0xFD0: case 0xFD1: case 0xFD2: case 0xFD3:
  3425.       case 0xFD4: case 0xFD5: case 0xFD6: case 0xFD7:
  3426.       case 0xFD8: case 0xFD9: case 0xFDA: case 0xFDB:
  3427.       case 0xFDC: case 0xFDD: case 0xFDE:
  3428.       case 0xFDF:
  3429.       case 0xFE0: case 0xFE1: case 0xFE2: case 0xFE3:
  3430.       case 0xFE4: case 0xFE5: case 0xFE6: case 0xFE7:
  3431.       case 0xFE8: case 0xFE9: case 0xFEA: case 0xFEB:
  3432.       case 0xFEC: case 0xFED: case 0xFEE:
  3433.       case 0xFEF:
  3434.       case 0xFF0: case 0xFF1: case 0xFF2: case 0xFF3:
  3435.       case 0xFF4: case 0xFF5: case 0xFF6: case 0xFF7:
  3436.       case 0xFF8: case 0xFF9: case 0xFFA: case 0xFFB:
  3437.       case 0xFFC: case 0xFFD: case 0xFFE:
  3438.       case 0xFFF:
  3439.         consume += isa_arm7_swi (agb, OP_code);
  3440.         break;
  3441.  
  3442.       case 0xA00: case 0xA01: case 0xA02: case 0xA03:
  3443.       case 0xA04: case 0xA05: case 0xA06: case 0xA07:
  3444.       case 0xA08: case 0xA09: case 0xA0A: case 0xA0B:
  3445.       case 0xA0C: case 0xA0D: case 0xA0E:
  3446.       case 0xA0F:
  3447.       case 0xA10: case 0xA11: case 0xA12: case 0xA13:
  3448.       case 0xA14: case 0xA15: case 0xA16: case 0xA17:
  3449.       case 0xA18: case 0xA19: case 0xA1A: case 0xA1B:
  3450.       case 0xA1C: case 0xA1D: case 0xA1E:
  3451.       case 0xA1F:
  3452.       case 0xA20: case 0xA21: case 0xA22: case 0xA23:
  3453.       case 0xA24: case 0xA25: case 0xA26: case 0xA27:
  3454.       case 0xA28: case 0xA29: case 0xA2A: case 0xA2B:
  3455.       case 0xA2C: case 0xA2D: case 0xA2E:
  3456.       case 0xA2F:
  3457.       case 0xA30: case 0xA31: case 0xA32: case 0xA33:
  3458.       case 0xA34: case 0xA35: case 0xA36: case 0xA37:
  3459.       case 0xA38: case 0xA39: case 0xA3A: case 0xA3B:
  3460.       case 0xA3C: case 0xA3D: case 0xA3E:
  3461.       case 0xA3F:
  3462.       case 0xA40: case 0xA41: case 0xA42: case 0xA43:
  3463.       case 0xA44: case 0xA45: case 0xA46: case 0xA47:
  3464.       case 0xA48: case 0xA49: case 0xA4A: case 0xA4B:
  3465.       case 0xA4C: case 0xA4D: case 0xA4E:
  3466.       case 0xA4F:
  3467.       case 0xA50: case 0xA51: case 0xA52: case 0xA53:
  3468.       case 0xA54: case 0xA55: case 0xA56: case 0xA57:
  3469.       case 0xA58: case 0xA59: case 0xA5A: case 0xA5B:
  3470.       case 0xA5C: case 0xA5D: case 0xA5E:
  3471.       case 0xA5F:
  3472.       case 0xA60: case 0xA61: case 0xA62: case 0xA63:
  3473.       case 0xA64: case 0xA65: case 0xA66: case 0xA67:
  3474.       case 0xA68: case 0xA69: case 0xA6A: case 0xA6B:
  3475.       case 0xA6C: case 0xA6D: case 0xA6E:
  3476.       case 0xA6F:
  3477.       case 0xA70: case 0xA71: case 0xA72: case 0xA73:
  3478.       case 0xA74: case 0xA75: case 0xA76: case 0xA77:
  3479.       case 0xA78: case 0xA79: case 0xA7A: case 0xA7B:
  3480.       case 0xA7C: case 0xA7D: case 0xA7E:
  3481.       case 0xA7F:
  3482.       case 0xA80: case 0xA81: case 0xA82: case 0xA83:
  3483.       case 0xA84: case 0xA85: case 0xA86: case 0xA87:
  3484.       case 0xA88: case 0xA89: case 0xA8A: case 0xA8B:
  3485.       case 0xA8C: case 0xA8D: case 0xA8E:
  3486.       case 0xA8F:
  3487.       case 0xA90: case 0xA91: case 0xA92: case 0xA93:
  3488.       case 0xA94: case 0xA95: case 0xA96: case 0xA97:
  3489.       case 0xA98: case 0xA99: case 0xA9A: case 0xA9B:
  3490.       case 0xA9C: case 0xA9D: case 0xA9E:
  3491.       case 0xA9F:
  3492.       case 0xAA0: case 0xAA1: case 0xAA2: case 0xAA3:
  3493.       case 0xAA4: case 0xAA5: case 0xAA6: case 0xAA7:
  3494.       case 0xAA8: case 0xAA9: case 0xAAA: case 0xAAB:
  3495.       case 0xAAC: case 0xAAD: case 0xAAE:
  3496.       case 0xAAF:
  3497.       case 0xAB0: case 0xAB1: case 0xAB2: case 0xAB3:
  3498.       case 0xAB4: case 0xAB5: case 0xAB6: case 0xAB7:
  3499.       case 0xAB8: case 0xAB9: case 0xABA: case 0xABB:
  3500.       case 0xABC: case 0xABD: case 0xABE:
  3501.       case 0xABF:
  3502.       case 0xAC0: case 0xAC1: case 0xAC2: case 0xAC3:
  3503.       case 0xAC4: case 0xAC5: case 0xAC6: case 0xAC7:
  3504.       case 0xAC8: case 0xAC9: case 0xACA: case 0xACB:
  3505.       case 0xACC: case 0xACD: case 0xACE:
  3506.       case 0xACF:
  3507.       case 0xAD0: case 0xAD1: case 0xAD2: case 0xAD3:
  3508.       case 0xAD4: case 0xAD5: case 0xAD6: case 0xAD7:
  3509.       case 0xAD8: case 0xAD9: case 0xADA: case 0xADB:
  3510.       case 0xADC: case 0xADD: case 0xADE:
  3511.       case 0xADF:
  3512.       case 0xAE0: case 0xAE1: case 0xAE2: case 0xAE3:
  3513.       case 0xAE4: case 0xAE5: case 0xAE6: case 0xAE7:
  3514.       case 0xAE8: case 0xAE9: case 0xAEA: case 0xAEB:
  3515.       case 0xAEC: case 0xAED: case 0xAEE:
  3516.       case 0xAEF:
  3517.       case 0xAF0: case 0xAF1: case 0xAF2: case 0xAF3:
  3518.       case 0xAF4: case 0xAF5: case 0xAF6: case 0xAF7:
  3519.       case 0xAF8: case 0xAF9: case 0xAFA: case 0xAFB:
  3520.       case 0xAFC: case 0xAFD: case 0xAFE:
  3521.       case 0xAFF:
  3522.         consume += isa_arm7_branch_without_link (agb, OP_code);
  3523.         break;
  3524.  
  3525.       case 0xB00: case 0xB01: case 0xB02: case 0xB03:
  3526.       case 0xB04: case 0xB05: case 0xB06: case 0xB07:
  3527.       case 0xB08: case 0xB09: case 0xB0A: case 0xB0B:
  3528.       case 0xB0C: case 0xB0D: case 0xB0E:
  3529.       case 0xB0F:
  3530.       case 0xB10: case 0xB11: case 0xB12: case 0xB13:
  3531.       case 0xB14: case 0xB15: case 0xB16: case 0xB17:
  3532.       case 0xB18: case 0xB19: case 0xB1A: case 0xB1B:
  3533.       case 0xB1C: case 0xB1D: case 0xB1E:
  3534.       case 0xB1F:
  3535.       case 0xB20: case 0xB21: case 0xB22: case 0xB23:
  3536.       case 0xB24: case 0xB25: case 0xB26: case 0xB27:
  3537.       case 0xB28: case 0xB29: case 0xB2A: case 0xB2B:
  3538.       case 0xB2C: case 0xB2D: case 0xB2E:
  3539.       case 0xB2F:
  3540.       case 0xB30: case 0xB31: case 0xB32: case 0xB33:
  3541.       case 0xB34: case 0xB35: case 0xB36: case 0xB37:
  3542.       case 0xB38: case 0xB39: case 0xB3A: case 0xB3B:
  3543.       case 0xB3C: case 0xB3D: case 0xB3E:
  3544.       case 0xB3F:
  3545.       case 0xB40: case 0xB41: case 0xB42: case 0xB43:
  3546.       case 0xB44: case 0xB45: case 0xB46: case 0xB47:
  3547.       case 0xB48: case 0xB49: case 0xB4A: case 0xB4B:
  3548.       case 0xB4C: case 0xB4D: case 0xB4E:
  3549.       case 0xB4F:
  3550.       case 0xB50: case 0xB51: case 0xB52: case 0xB53:
  3551.       case 0xB54: case 0xB55: case 0xB56: case 0xB57:
  3552.       case 0xB58: case 0xB59: case 0xB5A: case 0xB5B:
  3553.       case 0xB5C: case 0xB5D: case 0xB5E:
  3554.       case 0xB5F:
  3555.       case 0xB60: case 0xB61: case 0xB62: case 0xB63:
  3556.       case 0xB64: case 0xB65: case 0xB66: case 0xB67:
  3557.       case 0xB68: case 0xB69: case 0xB6A: case 0xB6B:
  3558.       case 0xB6C: case 0xB6D: case 0xB6E:
  3559.       case 0xB6F:
  3560.       case 0xB70: case 0xB71: case 0xB72: case 0xB73:
  3561.       case 0xB74: case 0xB75: case 0xB76: case 0xB77:
  3562.       case 0xB78: case 0xB79: case 0xB7A: case 0xB7B:
  3563.       case 0xB7C: case 0xB7D: case 0xB7E:
  3564.       case 0xB7F:
  3565.       case 0xB80: case 0xB81: case 0xB82: case 0xB83:
  3566.       case 0xB84: case 0xB85: case 0xB86: case 0xB87:
  3567.       case 0xB88: case 0xB89: case 0xB8A: case 0xB8B:
  3568.       case 0xB8C: case 0xB8D: case 0xB8E:
  3569.       case 0xB8F:
  3570.       case 0xB90: case 0xB91: case 0xB92: case 0xB93:
  3571.       case 0xB94: case 0xB95: case 0xB96: case 0xB97:
  3572.       case 0xB98: case 0xB99: case 0xB9A: case 0xB9B:
  3573.       case 0xB9C: case 0xB9D: case 0xB9E:
  3574.       case 0xB9F:
  3575.       case 0xBA0: case 0xBA1: case 0xBA2: case 0xBA3:
  3576.       case 0xBA4: case 0xBA5: case 0xBA6: case 0xBA7:
  3577.       case 0xBA8: case 0xBA9: case 0xBAA: case 0xBAB:
  3578.       case 0xBAC: case 0xBAD: case 0xBAE:
  3579.       case 0xBAF:
  3580.       case 0xBB0: case 0xBB1: case 0xBB2: case 0xBB3:
  3581.       case 0xBB4: case 0xBB5: case 0xBB6: case 0xBB7:
  3582.       case 0xBB8: case 0xBB9: case 0xBBA: case 0xBBB:
  3583.       case 0xBBC: case 0xBBD: case 0xBBE:
  3584.       case 0xBBF:
  3585.       case 0xBC0: case 0xBC1: case 0xBC2: case 0xBC3:
  3586.       case 0xBC4: case 0xBC5: case 0xBC6: case 0xBC7:
  3587.       case 0xBC8: case 0xBC9: case 0xBCA: case 0xBCB:
  3588.       case 0xBCC: case 0xBCD: case 0xBCE:
  3589.       case 0xBCF:
  3590.       case 0xBD0: case 0xBD1: case 0xBD2: case 0xBD3:
  3591.       case 0xBD4: case 0xBD5: case 0xBD6: case 0xBD7:
  3592.       case 0xBD8: case 0xBD9: case 0xBDA: case 0xBDB:
  3593.       case 0xBDC: case 0xBDD: case 0xBDE:
  3594.       case 0xBDF:
  3595.       case 0xBE0: case 0xBE1: case 0xBE2: case 0xBE3:
  3596.       case 0xBE4: case 0xBE5: case 0xBE6: case 0xBE7:
  3597.       case 0xBE8: case 0xBE9: case 0xBEA: case 0xBEB:
  3598.       case 0xBEC: case 0xBED: case 0xBEE:
  3599.       case 0xBEF:
  3600.       case 0xBF0: case 0xBF1: case 0xBF2: case 0xBF3:
  3601.       case 0xBF4: case 0xBF5: case 0xBF6: case 0xBF7:
  3602.       case 0xBF8: case 0xBF9: case 0xBFA: case 0xBFB:
  3603.       case 0xBFC: case 0xBFD: case 0xBFE:
  3604.       case 0xBFF:
  3605.         consume += isa_arm7_branch_with_link (agb, OP_code);
  3606.         break;
  3607.  
  3608. #define ALU_BLOCK(throat_alu, alu_cb, write_back, update_flags_cb, sign_bit)\
  3609.       case 0x200 | (throat_alu) << 5 | sign_bit << 4 | 0:\
  3610.       case 0x200 | (throat_alu) << 5 | sign_bit << 4 | 1:\
  3611.       case 0x200 | (throat_alu) << 5 | sign_bit << 4 | 2:\
  3612.       case 0x200 | (throat_alu) << 5 | sign_bit << 4 | 3:\
  3613.       case 0x200 | (throat_alu) << 5 | sign_bit << 4 | 4:\
  3614.       case 0x200 | (throat_alu) << 5 | sign_bit << 4 | 5:\
  3615.       case 0x200 | (throat_alu) << 5 | sign_bit << 4 | 6:\
  3616.       case 0x200 | (throat_alu) << 5 | sign_bit << 4 | 7:\
  3617.       case 0x200 | (throat_alu) << 5 | sign_bit << 4 | 8:\
  3618.       case 0x200 | (throat_alu) << 5 | sign_bit << 4 | 9:\
  3619.       case 0x200 | (throat_alu) << 5 | sign_bit << 4 |10:\
  3620.       case 0x200 | (throat_alu) << 5 | sign_bit << 4 |11:\
  3621.       case 0x200 | (throat_alu) << 5 | sign_bit << 4 |12:\
  3622.       case 0x200 | (throat_alu) << 5 | sign_bit << 4 |13:\
  3623.       case 0x200 | (throat_alu) << 5 | sign_bit << 4 |14:\
  3624.       case 0x200 | (throat_alu) << 5 | sign_bit << 4 |15:\
  3625.         consume += isa_arm7_alu_rot_imm32 (agb, OP_code, write_back, alu_cb, update_flags_cb, sign_bit); \
  3626.         break; \
  3627.       case (throat_alu) << 5 | sign_bit << 4 | 0: consume += isa_arm7_alu_shift_imm5 (agb, OP_code, 0, write_back, alu_cb, update_flags_cb, sign_bit); break; \
  3628.       case (throat_alu) << 5 | sign_bit << 4 | 2: consume += isa_arm7_alu_shift_imm5 (agb, OP_code, 1, write_back, alu_cb, update_flags_cb, sign_bit); break; \
  3629.       case (throat_alu) << 5 | sign_bit << 4 | 4: consume += isa_arm7_alu_shift_imm5 (agb, OP_code, 2, write_back, alu_cb, update_flags_cb, sign_bit); break; \
  3630.       case (throat_alu) << 5 | sign_bit << 4 | 6: consume += isa_arm7_alu_shift_imm5 (agb, OP_code, 3, write_back, alu_cb, update_flags_cb, sign_bit); break; \
  3631.       case (throat_alu) << 5 | sign_bit << 4 | 8: consume += isa_arm7_alu_shift_imm5 (agb, OP_code, 0, write_back, alu_cb, update_flags_cb, sign_bit); break; \
  3632.       case (throat_alu) << 5 | sign_bit << 4 |10:consume += isa_arm7_alu_shift_imm5 (agb, OP_code, 1, write_back, alu_cb, update_flags_cb, sign_bit); break; \
  3633.       case (throat_alu) << 5 | sign_bit << 4 |12:consume += isa_arm7_alu_shift_imm5 (agb, OP_code, 2, write_back, alu_cb, update_flags_cb, sign_bit); break; \
  3634.       case (throat_alu) << 5 | sign_bit << 4 |14:consume += isa_arm7_alu_shift_imm5 (agb, OP_code, 3, write_back, alu_cb, update_flags_cb, sign_bit); break; \
  3635.       case (throat_alu) << 5 | sign_bit << 4 | 1:consume += isa_arm7_alu_shift_rs (agb, OP_code, 0, write_back, alu_cb, update_flags_cb, sign_bit); break; \
  3636.       case (throat_alu) << 5 | sign_bit << 4 | 3:consume += isa_arm7_alu_shift_rs (agb, OP_code, 1, write_back, alu_cb, update_flags_cb, sign_bit); break; \
  3637.       case (throat_alu) << 5 | sign_bit << 4 | 5:consume += isa_arm7_alu_shift_rs (agb, OP_code, 2, write_back, alu_cb, update_flags_cb, sign_bit); break; \
  3638.       case (throat_alu) << 5 | sign_bit << 4 | 7:consume += isa_arm7_alu_shift_rs (agb, OP_code, 3, write_back, alu_cb, update_flags_cb, sign_bit); break; \
  3639.  
  3640.       ALU_BLOCK (0, alu_and, 1, update_flags_logic, 0)
  3641.       ALU_BLOCK (1, alu_eor, 1, update_flags_logic, 0)
  3642.       ALU_BLOCK (2, alu_sub, 1, update_flags_sub, 0)
  3643.       ALU_BLOCK (3, alu_rsb, 1, update_flags_sub, 0)
  3644.       ALU_BLOCK (4, alu_add, 1, update_flags_add, 0)
  3645.       ALU_BLOCK (5, alu_adc, 1, update_flags_add, 0)
  3646.       ALU_BLOCK (6, alu_sbc, 1, update_flags_sub, 0)
  3647.       ALU_BLOCK (7, alu_rsc, 1, update_flags_sub, 0)
  3648.       ALU_BLOCK (12, alu_orr, 1, update_flags_logic, 0)
  3649.       ALU_BLOCK (13, alu_mov, 1, update_flags_logic, 0)
  3650.       ALU_BLOCK (14, alu_bic, 1, update_flags_logic, 0)
  3651.       ALU_BLOCK (15, alu_mvn, 1, update_flags_logic, 0)
  3652.  
  3653.       ALU_BLOCK (0, alu_and, 1, update_flags_logic, 1)
  3654.       ALU_BLOCK (1, alu_eor, 1, update_flags_logic, 1)
  3655.       ALU_BLOCK (2, alu_sub, 1, update_flags_sub, 1)
  3656.       ALU_BLOCK (3, alu_rsb, 1, update_flags_sub, 1)
  3657.       ALU_BLOCK (4, alu_add, 1, update_flags_add, 1)
  3658.       ALU_BLOCK (5, alu_adc, 1, update_flags_add, 1)
  3659.       ALU_BLOCK (6, alu_sbc, 1, update_flags_sub, 1)
  3660.       ALU_BLOCK (7, alu_rsc, 1, update_flags_sub, 1)
  3661.       ALU_BLOCK (8, alu_and, 0, update_flags_logic, 1)
  3662.       ALU_BLOCK (9, alu_eor, 0, update_flags_logic, 1)
  3663.       ALU_BLOCK (10, alu_sub, 0, update_flags_sub, 1)
  3664.       ALU_BLOCK (11, alu_add, 0, update_flags_add, 1)
  3665.       ALU_BLOCK (12, alu_orr, 1, update_flags_logic, 1)
  3666.       ALU_BLOCK (13, alu_mov, 1, update_flags_logic, 1)
  3667.       ALU_BLOCK (14, alu_bic, 1, update_flags_logic, 1)
  3668.       ALU_BLOCK (15, alu_mvn, 1, update_flags_logic, 1)
  3669.  
  3670. #define LDR_SBH_BLOCK3(high5Bit)\
  3671.       case (high5Bit) << 4 | 11: \
  3672.         { const uint32_t throat_cache = (high5Bit) << 4 | 11; \
  3673.           const struct arm7_ldr_sbh_throat *const throat = (const struct arm7_ldr_sbh_throat *)& throat_cache;\
  3674.             if (throat->x == 0) \
  3675.               consume += isa_arm7_memory_access_sbh_reg (agb, OP_code, throat->p, throat->u, throat->w, throat->l, throat->s, throat->h);\
  3676.             else \
  3677.               consume += isa_arm7_memory_access_sbh_pad_imm8 (agb, OP_code, throat->p, throat->u, throat->w, throat->l, throat->s, throat->h);\
  3678.         }\
  3679.         break;\
  3680.       case (high5Bit) << 4 | 13: \
  3681.         { const uint32_t throat_cache = (high5Bit) << 4 | 13; \
  3682.           const struct arm7_ldr_sbh_throat *const throat = (const struct arm7_ldr_sbh_throat *)& throat_cache;\
  3683.             if (throat->x == 0) \
  3684.               consume += isa_arm7_memory_access_sbh_reg (agb, OP_code, throat->p, throat->u, throat->w, throat->l, throat->s, throat->h);\
  3685.             else \
  3686.               consume += isa_arm7_memory_access_sbh_pad_imm8 (agb, OP_code, throat->p, throat->u, throat->w, throat->l, throat->s, throat->h);\
  3687.         }\
  3688.         break;\
  3689.       case (high5Bit) << 4 | 15: \
  3690.         { const uint32_t throat_cache = (high5Bit) << 4 | 15; \
  3691.           const struct arm7_ldr_sbh_throat *const throat = (const struct arm7_ldr_sbh_throat *)& throat_cache;\
  3692.             if (throat->x == 0) \
  3693.               consume += isa_arm7_memory_access_sbh_reg (agb, OP_code, throat->p, throat->u, throat->w, throat->l, throat->s, throat->h);\
  3694.             else \
  3695.               consume += isa_arm7_memory_access_sbh_pad_imm8 (agb, OP_code, throat->p, throat->u, throat->w, throat->l, throat->s, throat->h);\
  3696.         }    \
  3697.       break;
  3698.      
  3699.         LDR_SBH_BLOCK3 (0)
  3700.         LDR_SBH_BLOCK3 (1)
  3701.         LDR_SBH_BLOCK3 (2)
  3702.         LDR_SBH_BLOCK3 (3)
  3703.         LDR_SBH_BLOCK3 (4)
  3704.         LDR_SBH_BLOCK3 (5)
  3705.         LDR_SBH_BLOCK3 (6)
  3706.         LDR_SBH_BLOCK3 (7)
  3707.         LDR_SBH_BLOCK3 (8)
  3708.         LDR_SBH_BLOCK3 (9)
  3709.         LDR_SBH_BLOCK3 (10)
  3710.         LDR_SBH_BLOCK3 (11)
  3711.         LDR_SBH_BLOCK3 (12)
  3712.         LDR_SBH_BLOCK3 (13)
  3713.         LDR_SBH_BLOCK3 (14)
  3714.         LDR_SBH_BLOCK3 (15)
  3715.         LDR_SBH_BLOCK3 (16)
  3716.         LDR_SBH_BLOCK3 (17)
  3717.         LDR_SBH_BLOCK3 (18)
  3718.         LDR_SBH_BLOCK3 (19)
  3719.         LDR_SBH_BLOCK3 (20)
  3720.         LDR_SBH_BLOCK3 (21)
  3721.         LDR_SBH_BLOCK3 (22)
  3722.         LDR_SBH_BLOCK3 (23)
  3723.         LDR_SBH_BLOCK3 (24)
  3724.         LDR_SBH_BLOCK3 (25)
  3725.         LDR_SBH_BLOCK3 (26)
  3726.         LDR_SBH_BLOCK3 (27)
  3727.         LDR_SBH_BLOCK3 (28)
  3728.         LDR_SBH_BLOCK3 (29)
  3729.         LDR_SBH_BLOCK3 (30)
  3730.         LDR_SBH_BLOCK3 (31)
  3731.  
  3732. #define LDR_UBW_BLOCK(const_throat, shift)\
  3733.         { const uint32_t _throat_t = const_throat;\
  3734.             const struct arm7_ldr_ubw_throat *const _throat  = (const struct arm7_ldr_ubw_throat *const) & _throat_t;\
  3735.             if (_throat->i != 0)\
  3736.               consume += isa_arm7_memory_access_ubw_scaled (agb, OP_code, shift, _throat->p, _throat->u, _throat->b, _throat->w, _throat->l);\
  3737.             else \
  3738.               consume += isa_arm7_memory_access_ubw_imm12 (agb, OP_code, _throat->p, _throat->u, _throat->b, _throat->w, _throat->l);\
  3739.         }\
  3740.         break;
  3741.  
  3742. #define LDR_UBW_BLOCK16(n)\
  3743.       case (0x400 | (n) << 4 | 0): LDR_UBW_BLOCK (n, 0 >> 1 & 3)\
  3744.       case (0x400 | (n) << 4 | 1): LDR_UBW_BLOCK (n, 1 >> 1 & 3)\
  3745.       case (0x400 | (n) << 4 | 2): LDR_UBW_BLOCK (n, 2 >> 1 & 3)\
  3746.       case (0x400 | (n) << 4 | 3): LDR_UBW_BLOCK (n, 3 >> 1 & 3)\
  3747.       case (0x400 | (n) << 4 | 4): LDR_UBW_BLOCK (n, 4 >> 1 & 3)\
  3748.       case (0x400 | (n) << 4 | 5): LDR_UBW_BLOCK (n, 5 >> 1 & 3)\
  3749.       case (0x400 | (n) << 4 | 6): LDR_UBW_BLOCK (n, 6 >> 1 & 3)\
  3750.       case (0x400 | (n) << 4 | 7): LDR_UBW_BLOCK (n, 7 >> 1 & 3)\
  3751.       case (0x400 | (n) << 4 | 8): LDR_UBW_BLOCK (n, 8 >> 1 & 3)\
  3752.       case (0x400 | (n) << 4 | 9): LDR_UBW_BLOCK (n, 9 >> 1 & 3)\
  3753.       case (0x400 | (n) << 4 |10): LDR_UBW_BLOCK (n, 10 >> 1 & 3)\
  3754.       case (0x400 | (n) << 4 |11): LDR_UBW_BLOCK (n, 11 >> 1 & 3)\
  3755.       case (0x400 | (n) << 4 |12): LDR_UBW_BLOCK (n, 12 >> 1 & 3)\
  3756.       case (0x400 | (n) << 4 |13): LDR_UBW_BLOCK (n, 13 >> 1 & 3)\
  3757.       case (0x400 | (n) << 4 |14): LDR_UBW_BLOCK (n, 14 >> 1 & 3)\
  3758.       case (0x400 | (n) << 4 |15): LDR_UBW_BLOCK (n, 15 >> 1 & 3)
  3759.  
  3760.         LDR_UBW_BLOCK16 (0)
  3761.         LDR_UBW_BLOCK16 (1)
  3762.         LDR_UBW_BLOCK16 (2)
  3763.         LDR_UBW_BLOCK16 (3)
  3764.         LDR_UBW_BLOCK16 (4)
  3765.         LDR_UBW_BLOCK16 (5)
  3766.         LDR_UBW_BLOCK16 (6)
  3767.         LDR_UBW_BLOCK16 (7)
  3768.         LDR_UBW_BLOCK16 (8)
  3769.         LDR_UBW_BLOCK16 (9)
  3770.         LDR_UBW_BLOCK16 (10)
  3771.         LDR_UBW_BLOCK16 (11)
  3772.         LDR_UBW_BLOCK16 (12)
  3773.         LDR_UBW_BLOCK16 (13)
  3774.         LDR_UBW_BLOCK16 (14)
  3775.         LDR_UBW_BLOCK16 (15)
  3776.         LDR_UBW_BLOCK16 (16)
  3777.         LDR_UBW_BLOCK16 (17)
  3778.         LDR_UBW_BLOCK16 (18)
  3779.         LDR_UBW_BLOCK16 (19)
  3780.         LDR_UBW_BLOCK16 (20)
  3781.         LDR_UBW_BLOCK16 (21)
  3782.         LDR_UBW_BLOCK16 (22)
  3783.         LDR_UBW_BLOCK16 (23)
  3784.         LDR_UBW_BLOCK16 (24)
  3785.         LDR_UBW_BLOCK16 (25)
  3786.         LDR_UBW_BLOCK16 (26)
  3787.         LDR_UBW_BLOCK16 (27)
  3788.         LDR_UBW_BLOCK16 (28)
  3789.         LDR_UBW_BLOCK16 (29)
  3790.         LDR_UBW_BLOCK16 (30)
  3791.         LDR_UBW_BLOCK16 (31)
  3792.         LDR_UBW_BLOCK16 (32)
  3793.         LDR_UBW_BLOCK16 (33)
  3794.         LDR_UBW_BLOCK16 (34)
  3795.         LDR_UBW_BLOCK16 (35)
  3796.         LDR_UBW_BLOCK16 (36)
  3797.         LDR_UBW_BLOCK16 (37)
  3798.         LDR_UBW_BLOCK16 (38)
  3799.         LDR_UBW_BLOCK16 (39)
  3800.         LDR_UBW_BLOCK16 (40)
  3801.         LDR_UBW_BLOCK16 (41)
  3802.         LDR_UBW_BLOCK16 (42)
  3803.         LDR_UBW_BLOCK16 (43)
  3804.         LDR_UBW_BLOCK16 (44)
  3805.         LDR_UBW_BLOCK16 (45)
  3806.         LDR_UBW_BLOCK16 (46)
  3807.         LDR_UBW_BLOCK16 (47)
  3808.         LDR_UBW_BLOCK16 (48)
  3809.         LDR_UBW_BLOCK16 (49)
  3810.         LDR_UBW_BLOCK16 (50)
  3811.         LDR_UBW_BLOCK16 (51)
  3812.         LDR_UBW_BLOCK16 (52)
  3813.         LDR_UBW_BLOCK16 (53)
  3814.         LDR_UBW_BLOCK16 (54)
  3815.         LDR_UBW_BLOCK16 (55)
  3816.         LDR_UBW_BLOCK16 (56)
  3817.         LDR_UBW_BLOCK16 (57)
  3818.         LDR_UBW_BLOCK16 (58)
  3819.         LDR_UBW_BLOCK16 (59)
  3820.         LDR_UBW_BLOCK16 (60)
  3821.         LDR_UBW_BLOCK16 (61)
  3822.         LDR_UBW_BLOCK16 (62)
  3823.         LDR_UBW_BLOCK16 (63)
  3824.  
  3825. #define LDM_BLOCK(const_throat) \
  3826.         { const uint32_t _throat_t = const_throat;\
  3827.             const struct arm7_ldm_throat *const _throat  = (const struct arm7_ldm_throat *const) & _throat_t;\
  3828.             if (_throat->l != 0)\
  3829.               consume += isa_arm7_list_memory_access_load (agb, OP_code, _throat->p, _throat->u, _throat->s, _throat->w);\
  3830.             else \
  3831.               consume += isa_arm7_list_memory_access_store (agb, OP_code, _throat->p, _throat->u, _throat->s, _throat->w);\
  3832.         }\
  3833.         break;
  3834.  
  3835. #define LDM_BLOCK16(n)\
  3836.       case (0x800 | (n) << 4 | 0): LDM_BLOCK (n)\
  3837.       case (0x800 | (n) << 4 | 1): LDM_BLOCK (n)\
  3838.       case (0x800 | (n) << 4 | 2): LDM_BLOCK (n)\
  3839.       case (0x800 | (n) << 4 | 3): LDM_BLOCK (n)\
  3840.       case (0x800 | (n) << 4 | 4): LDM_BLOCK (n)\
  3841.       case (0x800 | (n) << 4 | 5): LDM_BLOCK (n)\
  3842.       case (0x800 | (n) << 4 | 6): LDM_BLOCK (n)\
  3843.       case (0x800 | (n) << 4 | 7): LDM_BLOCK (n)\
  3844.       case (0x800 | (n) << 4 | 8): LDM_BLOCK (n)\
  3845.       case (0x800 | (n) << 4 | 9): LDM_BLOCK (n)\
  3846.       case (0x800 | (n) << 4 |10): LDM_BLOCK (n)\
  3847.       case (0x800 | (n) << 4 |11): LDM_BLOCK (n)\
  3848.       case (0x800 | (n) << 4 |12): LDM_BLOCK (n)\
  3849.       case (0x800 | (n) << 4 |13): LDM_BLOCK (n)\
  3850.       case (0x800 | (n) << 4 |14): LDM_BLOCK (n)\
  3851.       case (0x800 | (n) << 4 |15): LDM_BLOCK (n)
  3852.  
  3853.         LDM_BLOCK16 (0)
  3854.         LDM_BLOCK16 (1)
  3855.         LDM_BLOCK16 (2)
  3856.         LDM_BLOCK16 (3)
  3857.         LDM_BLOCK16 (4)
  3858.         LDM_BLOCK16 (5)
  3859.         LDM_BLOCK16 (6)
  3860.         LDM_BLOCK16 (7)
  3861.         LDM_BLOCK16 (8)
  3862.         LDM_BLOCK16 (9)
  3863.         LDM_BLOCK16 (10)
  3864.         LDM_BLOCK16 (11)
  3865.         LDM_BLOCK16 (12)
  3866.         LDM_BLOCK16 (13)
  3867.         LDM_BLOCK16 (14)
  3868.         LDM_BLOCK16 (15)
  3869.         LDM_BLOCK16 (16)
  3870.         LDM_BLOCK16 (17)
  3871.         LDM_BLOCK16 (18)
  3872.         LDM_BLOCK16 (19)
  3873.         LDM_BLOCK16 (20)
  3874.         LDM_BLOCK16 (21)
  3875.         LDM_BLOCK16 (22)
  3876.         LDM_BLOCK16 (23)
  3877.         LDM_BLOCK16 (24)
  3878.         LDM_BLOCK16 (25)
  3879.         LDM_BLOCK16 (26)
  3880.         LDM_BLOCK16 (27)
  3881.         LDM_BLOCK16 (28)
  3882.         LDM_BLOCK16 (29)
  3883.         LDM_BLOCK16 (30)
  3884.         LDM_BLOCK16 (31)
  3885.       default:
  3886.         assert (0);
  3887.       }
  3888.       regs[15] += 4;
  3889.     }
  3890.     break;
  3891.   } while (0);
  3892.  
  3893.   return consume;
  3894. }
  3895.  
  3896. #endif
Advertisement
Add Comment
Please, Sign In to add comment
Advertisement
Public Pastes
Advertisement
We use cookies for various purposes including analytics. By continuing to use Pastebin, you agree to our use of cookies as described in the Cookies Policy.  OK, I Understand
Not a member of Pastebin yet?
Sign Up, it unlocks many cool features!