;*******************************************************************
;Port definitions
;*******************************************************************
;
CONSTANT LED_port, 80 ;8 simple LEDs
CONSTANT LED0, 01 ; LED 0 - bit0
CONSTANT LED1, 02 ; 1 - bit1
CONSTANT LED2, 04 ; 2 - bit2
CONSTANT LED3, 08 ; 3 - bit3
CONSTANT LED4, 10 ; 4 - bit4
CONSTANT LED5, 20 ; 5 - bit5
CONSTANT LED6, 40 ; 6 - bit6
CONSTANT LED7, 80 ; 7 - bit7
;
CONSTANT switch_port, 00 ;Read switches and press buttons
CONSTANT switch0, 01 ; Switches SW0 - bit0
CONSTANT switch1, 02 ; SW1 - bit1
CONSTANT switch2, 04 ; SW2 - bit2
CONSTANT switch3, 08 ; SW3 - bit3
CONSTANT BTN_east, 10 ; Buttons East - bit4
CONSTANT BTN_south, 20 ; South - bit5
CONSTANT BTN_north, 40 ; North - bit6
CONSTANT BTN_west, 80 ; West - bit7
;
;
;LCD interface ports
;
;The master enable signal is not used by the LCD display itself
;but may be required to confirm that LCD communication is active.
;This is required on the Spartan-3E Starter Kit if the StrataFLASH
;is used because it shares the same data pins and conflicts must be
;avoided.
;
CONSTANT LCD_output_port, 40 ;LCD character module output
 ;data and control
CONSTANT LCD_E, 01 ; active High Enable E - bit0
CONSTANT LCD_RW, 02 ; Read=1 Write=0 RW - bit1
CONSTANT LCD_RS, 04 ; Instruction=0 Data=1 RS - bit2
CONSTANT LCD_drive, 08 ; Master enable (active High)
 ; - bit3
CONSTANT LCD_DB4, 10 ; 4-bit Data DB4 - bit4
CONSTANT LCD_DB5, 20 ; interface Data DB5 - bit5
CONSTANT LCD_DB6, 40 ; Data DB6 - bit6
CONSTANT LCD_DB7, 80 ; Data DB7 - bit7
;
;
CONSTANT LCD_input_port, 02 ;LCD character module input data
CONSTANT LCD_read_spare0, 01 ; Spare bits - bit0
CONSTANT LCD_read_spare1, 02 ; are zero - bit1
CONSTANT LCD_read_spare2, 04 ; - bit2
CONSTANT LCD_read_spare3, 08 ; - bit3
CONSTANT LCD_read_DB4, 10 ; 4-bit Data DB4 - bit4
CONSTANT LCD_read_DB5, 20 ; interface Data DB5 - bit5
CONSTANT LCD_read_DB6, 40 ; Data DB6 - bit6
CONSTANT LCD_read_DB7, 80 ; Data DB7 - bit7
;
;



Xilinx Spartan-3E Project Navigator Version 14.3
;Constant to define a software delay of 1us. This must be adjusted
;to reflect the clock applied to KCPSM3. Every instruction executes
;in 2 clock cycles making the calculation highly predictable. The
;'6' in the following equation even allows for 'CALL delay_1us'
;instruction in the initiating code.
;
;delay_1us_constant = (clock_rate - 6)/4 Where 'clock_rate'
;is in MHz
;
;Example: For a 50MHz clock the constant value is (10-6)/4 = 11
;(0B Hex).
;For clock rates below 10MHz the value of 1 must be used and the
;operation will become lower than intended.
;
CONSTANT delay_1us_constant, 0B
;

 ;
 ;*******************************************
 ;Initialise the system
 ;*******************************************
 ;
 cold_start: CALL LCD_reset ;initialise LCD display
 ;
 Main: INPUT s7, switch_port ;read in switches
 OUTPUT s7, LED_port ;output to LEDs
 JUMP Main
 ;
 ;

 ;
 ;*******************************************
 ;Software delay routines
 ;*******************************************
 ;
 ;
 ;Delay of 1us.
 ;
 ;Constant value defines reflects the clock applied
 ;to KCPSM3. Every instruction executes in 2 clock
 ;cycles making the calculation highly predictable.
 ;The '6' in the following equation even allows for
 ;'CALL delay_1us' instruction in the initiating code.
 ;
 ; delay_1us_constant = (clock_rate - 6)/4
 ; Where 'clock_rate' is in MHz
 ;
 ;Registers used s0
 ;
 delay_1us: LOAD s0, delay_1us_constant
 wait_1us: SUB s0, 01
 JUMP NZ, wait_1us
 RETURN
 ;
 ;Delay of 40us.
 ;
 ;Registers used s0, s1
 ;


Xilinx Spartan-3E Project Navigator Version 14.3
 delay_40us: LOAD s1, 28 ;40 x 1us = 40us
 wait_40us: CALL delay_1us
 SUB s1, 01
 JUMP NZ, wait_40us
 RETURN
 ;
 ;
 ;Delay of 1ms.
 ;
 ;Registers used s0, s1, s2
 ;
 delay_1ms: LOAD s2, 19 ;25 x 40us = 1ms
 wait_1ms: CALL delay_40us
 SUB s2, 01
 JUMP NZ, wait_1ms
 RETURN
 ;
 ;Delay of 20ms.
 ;
 ;Delay of 20ms used during initialisation.
 ;
 ;Registers used s0, s1, s2, s3
 ;
 delay_20ms: LOAD s3, 14 ;20 x 1ms = 20ms
 wait_20ms: CALL delay_1ms
 SUB s3, 01
 JUMP NZ, wait_20ms
 RETURN
 ;
 ;Delay of approximately 1 second.
 ;
 ;Registers used s0, s1, s2, s3, s4
 ;
 delay_1s: LOAD s4, 32 ;50 x 20ms = 1000ms
 wait_1s: CALL delay_20ms
 SUB s4, 01
 JUMP NZ, wait_1s
 RETURN
 ;

 ;
 ;
 ;**************************************************
 ;LCD Character Module Routines
 ;**************************************************
 ;
 ;LCD module is a 16 character by 2 line display but
 ;all displays are very similar The 4-wire data
 ;interface will be used (DB4 to DB7).
 ;
 ;The LCD modules are relatively slow and software
 ;delay loops are used to slow down KCPSM3
 ;adequately for the LCD to communicate. The delay
 ;routines are provided in a different section (see
 ;above in this case).
 ;
 ;


Xilinx Spartan-3E Project Navigator Version 14.3
 ;Pulse LCD enable signal 'E' high for greater than
 ;230ns (1us is used).
 ;
 ;Register s4 should define the current state of the
 ;LCD output port.
 ;
 ;Registers used s0, s4
 ;
 LCD_pulse_E: XOR s4, LCD_E ;E=1
 OUTPUT s4, LCD_output_port
 CALL delay_1us
 XOR s4, LCD_E ;E=0
 OUTPUT s4, LCD_output_port
 RETURN
 ;
 ;Write 4-bit instruction to LCD display.
 ;
 ;The 4-bit instruction should be provided in the
 ;upper 4-bits of register s4.
 ;Note that this routine does not release the master
 ;enable but as it is only
 ;used during initialisation and as part of the
 ;8-bit instruction write it should be acceptable.
 ;
 ;Registers used s4
 ;
LCD_write_inst4: AND s4, F8 ;Enable=1 RS=0
 ;Instruction, RW=0
 ;Write, E=0
 ;
 OUTPUT s4, LCD_output_port ;set up RS and RW>40ns
 ;before enable pulse
 ;
 CALL LCD_pulse_E
 RETURN
 ;
 ;
 ;Write 8-bit instruction to LCD display.
 ;
 ;The 8-bit instruction should be provided in
 ; register s5.
 ;Instructions are written using the following
 ;sequence
 ; Upper nibble
 ; wait >1us
 ; Lower nibble
 ; wait >40us
 ;
 ;Registers used s0, s1, s4, s5
 ;
LCD_write_inst8: LOAD s4, s5
 AND s4, F0 ;Enable=0 RS=0
 ;Instruction, RW=0
 ;Write, E=0
 ;


Xilinx Spartan-3E Project Navigator Version 14.3
 OR s4, LCD_drive ;Enable=1
 CALL LCD_write_inst4 ;write upper nibble
 CALL delay_1us ;wait >1us
 LOAD s4, s5 ;select lower nibble
 ;with
 SL1 s4 ;Enable=1
 SL0 s4 ;RS=0 Instruction
 SL0 s4 ;RW=0 Write
 SL0 s4 ;E=0
 CALL LCD_write_inst4 ;write lower nibble
 CALL delay_40us ;wait >40us
 LOAD s4, F0 ;Enable=0 RS=0
 ;Instruction, RW=0
 ;Write, E=0
 ;
 OUTPUT s4, LCD_output_port ;Release master enable
 ;
 RETURN
 ;
 ;Write 8-bit data to LCD display.
 ;
 ;The 8-bit data should be provided in register s5.
 ;Data bytes are written using the following sequence
 ; Upper nibble
 ; wait >1us
 ; Lower nibble
 ; wait >40us
 ;
 ;Registers used s0, s1, s4, s5
 ;
 LCD_write_data: LOAD s4, s5
 AND s4, F0 ;Enable=0 RS=0
 ;Instruction, RW=0
 ;Write, E=0
 ;
 OR s4, 0C ;Enable=1 RS=1 Data,
 ;RW=0 Write, E=0
 ;
 OUTPUT s4, LCD_output_port ;set up RS and RW>40ns
 ;before enable pulse
 ;
 CALL LCD_pulse_E ;write upper nibble
 CALL delay_1us ;wait >1us
 LOAD s4, s5 ;select lower nibble
 ;with
 SL1 s4 ;Enable=1
 SL1 s4 ;RS=1 Data
 SL0 s4 ;RW=0 Write
 SL0 s4 ;E=0
 OUTPUT s4, LCD_output_port ;set up RS and RW>40ns
 ;before enable pulse
 ;
 CALL LCD_pulse_E ;write lower nibble
 CALL delay_40us ;wait >40us
 LOAD s4, F0 ;Enable=0 RS=0
 ;Instruction, RW=0
 ;Write, E=0


Xilinx Spartan-3E Project Navigator Version 14.3
 ;
 OUTPUT s4, LCD_output_port ;Release master enable
 ;
 RETURN
 ;
 ;Read 8-bit data from LCD display.
 ;
 ;The 8-bit data will be read from the current LCD
 ;memory address and will be returned in register s5.
 ;It is advisable to set the LCD address (cursor
 ;position) before using the data read for the first
 ;time otherwise the display may generate invalid data
 ;on the first read.
 ;
 ;Data bytes are read using the following sequence
 ; Upper nibble
 ; wait >1us
 ; Lower nibble
 ; wait >40us
 ;
 ;Registers used s0, s1, s4, s5
 ;
 LCD_read_data8: LOAD s4, 0E ;Enable=1 RS=1 Data,
 ;RW=1 Read, E=0
 ;
 OUTPUT s4, LCD_output_port ;set up RS and RW>40ns
 ;before enable pulse
 ;
 XOR s4, LCD_E ;E=1
 OUTPUT s4, LCD_output_port
 CALL delay_1us ;wait >260ns to
 ;access data
 ;
 INPUT s5, LCD_input_port ;read upper nibble
 XOR s4, LCD_E ;E=0
 OUTPUT s4, LCD_output_port
 CALL delay_1us ;wait >1us
 XOR s4, LCD_E ;E=1
 OUTPUT s4, LCD_output_port
 CALL delay_1us ;wait >260ns to
 ;access data
 ;
 INPUT s0, LCD_input_port ;read lower nibble
 XOR s4, LCD_E ;E=0
 OUTPUT s4, LCD_output_port
 AND s5, F0 ;merge upper and
 ;lower nibbles
 SR0 s0
 SR0 s0
 SR0 s0
 SR0 s0
 OR s5, s0
 LOAD s4, 04 ;Enable=0 RS=1 Data,
 ;RW=0 Write, E=0
 ;


Xilinx Spartan-3E Project Navigator Version 14.3
 OUTPUT s4, LCD_output_port ;Stop reading 5V
 ;device and release
 ;master enable
 ;
 CALL delay_40us ;wait >40us
 RETURN
 ;
 ;Reset and initialise display to communicate using
 ;4-bit data mode
 ;Includes routine to clear the display.
 ;
 ;Requires the 4-bit instructions 3,3,3,2 to be sent
 ;with suitable delays following by the 8-bit
 ;instructions to set up the display.
 ;
 ; 28 = '001' Function set, '0' 4-bit mode, '1' 2-line,
 ; '0' 5x7 dot matrix, 'xx'
 ; 06 = '000001' Entry mode, '1' increment, '0'
 ; no display shift
 ; 0C = '00001' Display control, '1' display on,
 ; '0' cursor off, '0' cursor blink off
 ; 01 = '00000001' Display clear
 ;
 ;Registers used s0, s1, s2, s3, s4
 ;
 LCD_reset: CALL delay_20ms ;wait more that
 ;15ms for display
 ;to be ready
 ;
 LOAD s4, 30
 CALL LCD_write_inst4 ;send '3'
 CALL delay_20ms ;wait >4.1ms
 CALL LCD_write_inst4 ;send '3'
 CALL delay_1ms ;wait >100us
 CALL LCD_write_inst4 ;send '3'
 CALL delay_40us ;wait >40us
 LOAD s4, 20
 CALL LCD_write_inst4 ;send '2'
 CALL delay_40us ;wait >40us
 LOAD s5, 28 ;Function set
 CALL LCD_write_inst8
 LOAD s5, 06 ;Entry mode
 CALL LCD_write_inst8
 LOAD s5, 0C ;Display control
 CALL LCD_write_inst8
 LCD_clear: LOAD s5, 01 ;Display clear
 CALL LCD_write_inst8
 CALL delay_1ms ;wait >1.64ms for
 ;display to clear
 CALL delay_1ms
 RETUR