ssc5ADDN

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-- Company:
-- Engineer:
--
-- Create Date: 03/30/2018 03:05:32 PM
-- Design Name:
-- Module Name: ADDN - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;


entity ADDN is
generic (N:integer);
Port (X :in std_logic_vector(N-1 downto 0);
      Y:in std_logic_vector(N-1 downto 0);
      Tin:in std_logic;
      S:out std_logic_vector(N-1 downto 0);
      OVF:out std_logic;
      Tout:out std_logic);
end ADDN;

architecture Behavioral of ADDN is
signal T :std_logic_vector(N downto 0);
begin
    T(0)<=Tin;

    process(X,Y,Tin)
        begin
            for i in 0 to N-1 loop
                S(i)<=X(i) xor Y(i) xor T(i);
                T(i+1)<=(X(i) and Y(i)) or ((X(i) or Y(i)) and T(i));
            end loop;
            Tout<=T(N);
            OVF<=T(N) xor T(N-1);
    end process;
end Behavioral;