LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
ENTITY FAMAKIN_2_STAGE_ADDER IS
 GENERIC(P: integer:= 16;
W: integer:= 4;
 E: integer:= 8);
PORT ( CLK :IN STD_LOGIC; --clk
Reset :IN STD_LOGIC; --reset
En :IN STD_LOGIC;
Op_A :IN STD_LOGIC_VECTOR(P-1 DOWNTO 0);
Op_B :IN STD_LOGIC_VECTOR(P-1 DOWNTO 0);
Op_Q :OUT STD_LOGIC_VECTOR(P-1 DOWNTO 0);
Op_F :OUT STD_LOGIC_VECTOR(W-2 DOWNTO 0)
 );
END FAMAKIN_2_STAGE_ADDER;

ARCHITECTURE STRUCTURAL OF FAMAKIN_2_STAGE_ADDER IS
COMPONENT FAMAKIN_First_BSlice
PORT (
Op_A :IN STD_LOGIC;
Op_B :IN STD_LOGIC;
SUM_Q :OUT STD_LOGIC;
Carry_Q :OUT STD_LOGIC
 );
END COMPONENT;
COMPONENT FAMAKIN_FA_BSlice
PORT (
Op_A :IN STD_LOGIC;
Op_B :IN STD_LOGIC;
Op_C :IN STD_LOGIC;
SUM_Q :OUT STD_LOGIC;
Carry_Q :OUT STD_LOGIC
 );
END COMPONENT;


COMPONENT REG_FA
 GENERIC(P: integer:= 16;
 W: integer:= 4;
 E: integer:= 8);
PORT ( CLK :IN STD_LOGIC; --clk
Reset :IN STD_LOGIC; --reset
En :IN STD_LOGIC;
Op_A :IN STD_LOGIC_VECTOR(P-1 DOWNTO 0);
Op_B :IN STD_LOGIC_VECTOR(P-1 DOWNTO 0);
Op_Sum :IN STD_LOGIC_VECTOR(W-1 DOWNTO 0); -- sum
Op_Carry:IN STD_LOGIC; -- carry
Op_AQ :OUT STD_LOGIC_VECTOR(P-1 DOWNTO 0);
Op_BQ :OUT STD_LOGIC_VECTOR(P-1 DOWNTO 0);
Op_SQ :OUT STD_LOGIC_VECTOR(W-1 DOWNTO 0);
Op_C :OUT STD_LOGIC
 );
END COMPONENT;


COMPONENT REG_FA_lastslice
 GENERIC(P: integer:= 16;
 W: integer:= 4;
 E: integer:= 8);
PORT ( CLK :IN STD_LOGIC; --clk
Reset :IN STD_LOGIC; --reset
En :IN STD_LOGIC;
Op_A :IN STD_LOGIC; -- sign bit
Op_B :IN STD_LOGIC; -- sign bit
Op_Sum :IN STD_LOGIC_VECTOR(P-1 DOWNTO 0); -- sum
Op_Carry:IN STD_LOGIC; -- carry
Op_Q :OUT STD_LOGIC_VECTOR(P-1 DOWNTO 0);
Op_F :OUT STD_LOGIC_VECTOR(W-2 DOWNTO 0)
 );
END COMPONENT;

SIGNAL S_A1: STD_LOGIC_VECTOR(2*W-1 DOWNTO 0);
SIGNAL S_B1: STD_LOGIC_VECTOR(2*W-1 DOWNTO 0);

SIGNAL SUM_Q1: STD_LOGIC_VECTOR(2*W-1 DOWNTO 0);
SIGNAL SUM_Q2: STD_LOGIC_VECTOR(4*W-1 DOWNTO 0);

SIGNAL SOP_C1: STD_LOGIC;
SIGNAL SOP_C2: STD_LOGIC;
SIGNAL SOP_C3: STD_LOGIC;
SIGNAL SOP_C4: STD_LOGIC;
SIGNAL SOP_C5: STD_LOGIC;
SIGNAL SOP_C6: STD_LOGIC;
SIGNAL SOP_C7: STD_LOGIC;
SIGNAL SOP_C8: STD_LOGIC;
SIGNAL SOP_C9: STD_LOGIC;
SIGNAL SOP_C10: STD_LOGIC;
SIGNAL SOP_C11: STD_LOGIC;
SIGNAL SOP_C12: STD_LOGIC;
SIGNAL SOP_C13: STD_LOGIC;
SIGNAL SOP_C14: STD_LOGIC;
SIGNAL SOP_C15: STD_LOGIC;
SIGNAL SOP_C16: STD_LOGIC;
SIGNAL SOP_C17: STD_LOGIC;

BEGIN
A1: FAMAKIN_First_BSlice
PORT MAP(Op_A(W-4), Op_B(W-4), SUM_Q1(W-4),SOP_C1);
A2: FAMAKIN_FA_BSlice
PORT MAP(Op_A(W-3), Op_B(W-3), SOP_C1, SUM_Q1(W-3), SOP_C2);
A3: FAMAKIN_FA_BSlice
PORT MAP(Op_A(W-2), Op_B(W-2), SOP_C2, SUM_Q1(W-2), SOP_C3);
A4: FAMAKIN_FA_BSlice
PORT MAP(Op_A(W-1), Op_B(W-1), SOP_C3, SUM_Q1(W-1), SOP_C4);
A5: FAMAKIN_FA_BSlice
PORT MAP(Op_A(W), Op_B(W), SOP_C4, SUM_Q1(W), SOP_C5);
A6: FAMAKIN_FA_BSlice
PORT MAP(Op_A(W+1), Op_B(W+1), SOP_C5, SUM_Q1(W+1), SOP_C6);
A7: FAMAKIN_FA_BSlice
PORT MAP(Op_A(W+2), Op_B(W+2), SOP_C6, SUM_Q1(W+2), SOP_C7);
A8: FAMAKIN_FA_BSlice
PORT MAP(Op_A(W+3), Op_B(W+3), SOP_C7, SUM_Q1(W+3), SOP_C8);
A9: REG_FA GENERIC MAP(P-2*W, 2*W, E)
PORT MAP(Clk, Reset, En, Op_A(P-1 DOWNTO 2*W), Op_B(P-1 DOWNTO
2*W), SUM_Q1, SOP_C8, S_A1, S_B1, SUM_Q2(2*W-1 DOWNTO 0), SOP_C9);


B1: FAMAKIN_FA_BSlice
PORT MAP(S_A1(W-4), S_B1(W-4), SOP_C9, SUM_Q2(2*W), SOP_C10);
B2: FAMAKIN_FA_BSlice
PORT MAP(S_A1(W-3), S_B1(W-3), SOP_C10, SUM_Q2(2*W+1), SOP_C11);
B3: FAMAKIN_FA_BSlice
PORT MAP(S_A1(W-2), S_B1(W-2), SOP_C11, SUM_Q2(2*W+2), SOP_C12);
B4: FAMAKIN_FA_BSlice
PORT MAP(S_A1(W-1), S_B1(W-1), SOP_C12, SUM_Q2(2*W+3), SOP_C13);
B5: FAMAKIN_FA_BSlice
PORT MAP(S_A1(W), S_B1(W), SOP_C13, SUM_Q2(3*W), SOP_C14);
B6: FAMAKIN_FA_BSlice
PORT MAP(S_A1(W+1), S_B1(W+1), SOP_C14, SUM_Q2(3*W+1), SOP_C15);
B7: FAMAKIN_FA_BSlice
PORT MAP(S_A1(W+2), S_B1(W+2), SOP_C15, SUM_Q2(3*W+2), SOP_C16);
B8: FAMAKIN_FA_BSlice
PORT MAP(S_A1(W+3), S_B1(W+3), SOP_C16, SUM_Q2(3*W+3), SOP_C17);
B9: REG_FA_lastslice GENERIC MAP(P, W, E)
PORT MAP(Clk, Reset, En, S_A1(2*W-1), S_B1(2*W-1),SUM_Q2, SUM_Q2(P-1), OP_Q,
OP_F);
END STRUCTURAL;