tlv320regs

enum page0_registers{
  Page_Select_Register=0,
  Software_Reset_Register=1,
  Codec_Sample_Rate_Select_Register=2,
  PLL_Programming_Register_A=3,
  PLL_Programming_Register_B=4,
  PLL_Programming_Register_C=5,
  PLL_Programming_Register_D=6,
  Codec_Data_Path_Setup_Register=7,
  Audio_Serial_Data_Interface_Control_Register_A=8,
  Audio_Serial_Data_Interface_Control_Register_B=9,
  Audio_Serial_Data_Interface_Control_Register_C=10,
  Audio_Codec_Overflow_Flag_Register=11,
  Audio_Codec_Digital_Filter_Control_Register=12,
  Headset,_Button_Press_Detection_Register_A=13,
  Headset,_Button_Press_Detection_Register_B=14,
  Left_ADC_PGA_Gain_Control_Register=15,
  Right_ADC_PGA_Gain_Control_Register=16,
  MIC2L_R_to_Left_ADC_Control_Register=17,
  MIC2_LINE2_to_Right_ADC_Control_Register=18,
  MIC1LP_LINE1LP_to_Left_ADC_Control_Register=19,
  MIC1RP_LINE1RP_to_Left_ADC_Control_Register=21,
  MIC1RP_LINE1RP_to_Right_ADC_Control_Register=22,
  MIC1LP_LINE1LP_to_Right_ADC_Control_Register=24,
  MICBIAS_Control_Register=25,
  Left_AGC_Control_Register_A=26,
  Left_AGC_Control_Register_B=27,
  Left_AGC_Control_Register_C=28,
  Right_AGC_Control_Register_A=29,
  Right_AGC_Control_Register_B=30,
  Right_AGC_Control_Register_C=31,
  Left_AGC_Gain_Register=32,
  Right_AGC_Gain_Register=33,
  Left_AGC_Noise_Gate_Debounce_Register=34,
  Right_AGC_Noise_Gate_Debounce_Register=35,
  ADC_Flag_Register=36,
  DAC_Power_and_Output_Driver_Control_Register=37,
  High_Power_Output_Driver_Control_Register=38,
  High_Power_Output_Stage_Control_Register=40,
  DAC_Output_Switching_Control_Register=41,
  Output_Driver_Pop_Reduction_Register=42,
  Left_DAC_Digital_Volume_Control_Register=43,
  Right_DAC_Digital_Volume_Control_Register=44,
  PGA_L_to_HPLOUT_Volume_Control_Register=46,
  DAC_L1_to_HPLOUT_Volume_Control_Register=47,
  PGA_R_to_HPLOUT_Volume_Control_Register=49,
  DAC_R1_to_HPLOUT_Volume_Control_Register=50,
  HPLOUT_Output_Level_Control_Register=51,
  PGA_L_to_HPLCOM_Volume_Control_Register=53,
  DAC_L1_to_HPLCOM_Volume_Control_Register=54,
  PGA_R_to_HPLCOM_Volume_Control_Register=56,
  DAC_R1_to_HPLCOM_Volume_Control_Register=57,
  HPLCOM_Output_Level_Control_Register=58,
  PGA_L_to_HPROUT_Volume_Control_Register=60,
  DAC_L1_to_HPROUT_Volume_Control_Register=61,
  PGA_R_to_HPROUT_Volume_Control_Register=63,
  DAC_R1_to_HPROUT_Volume_Control_Register=64,
  HPROUT_Output_Level_Control_Register=65,
  PGA_L_to_HPRCOM_Volume_Control_Register=67,
  DAC_L1_to_HPRCOM_Volume_Control_Register=68,
  PGA_R_to_HPRCOM_Volume_Control_Register=70,
  DAC_R1_to_HPRCOM_Volume_Control_Register=71,
  HPRCOM_Output_Level_Control_Register=72,
  PGA_L_to_LEFT_LOP_M_Volume_Control_Register=81,
  DAC_L1_to_LEFT_LOP_M_Volume_Control_Register=82,
  PGA_R_to_LEFT_LOP_M_Volume_Control_Register=84,
  DAC_R1_to_LEFT_LOP_M_Volume_Control_Register=85,
  LEFT_LOP_M_Output_Level_Control_Register=86,
  PGA_L_to_RIGHT_LOP_M_Volume_Control_Register=88,
  DAC_L1_to_RIGHT_LOP_M_Volume_Control_Register=89,
  PGA_R_to_RIGHT_LOP_M_Volume_Control_Register=91,
  DAC_R1_to_RIGHT_LOP_M_Volume_Control_Register=92,
  RIGHT_LOP_M_Output_Level_Control_Register=93,
  Module_Power_Status_Register=94,
  Output_Driver_Short_Circuit_Detection_Status_Register=95,
  Sticky_Interrupt_Flags_Register=96,
  Real_Time_Interrupt_Flags_Register=97,
  Clock_Register=101,
  Clock_Generation_Control_Register=102,
  Left_AGC_New_Programmable_Attack_Time_Register=103,
  Left_AGC_New_Programmable_Decay_Time_Register=104,
  Right_AGC_New_Programmable_Attack_Time_Register=105,
  Right_AGC_New_Programmable_Decay_Time_Register=106,
  New_Programmable_ADC_Digital_Path_and_I2C_Bus_Condition_Register=107,
  Passive_Analog_Signal_Bypass_Selection_During_Power_Down_Register=108,
  DAC_Quiescent_Current_Adjustment_Register=109
};