lab8_del2

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity TB is
  port(
    CLOCK_50 : in    std_logic;
    KEY      : in    std_logic_vector(3 downto 0);
    SW       : in    std_logic_vector(17 downto 0);
    GPIO     : inout std_logic_vector(35 downto 0);
    LEDR     : out   std_logic_vector(17 downto 0);
    LEDG     : out   std_logic_vector(7 downto 0)
    );
end entity TB;

architecture RTL of TB is

  component Enable_gen is
    port(clock_50    : in  std_logic;
         resetn      : in  std_logic;
         velg_enable : in  std_logic_vector(2 downto 0);
         Enable      : out std_logic);
  end component;

  component reset_synchronizer is
    port(
      clk        : in  std_logic;
      reset_key3 : in  std_logic;
      reset_clk  : out std_logic
      );
  end component reset_synchronizer;

  component baudrate_gen is
    port(
      CLOCK_50      : in std_logic;
      resetn        : in std_logic;
      velg_baudrate : in std_logic_vector(2 downto 0);
      start_teller  : in std_logic;

      baud_enable_m : out std_logic;
      baud_enable_s : out std_logic
      );
  end component baudrate_gen;

  signal resetn                                          : std_logic;
  signal hallo_enable                                    : std_logic;
  signal hallo                                           : std_logic;
  signal sender                                          : std_logic;
  signal mottatt_blink                                   : std_logic;
  signal vippe_a, vippe_b                                : std_logic;
  signal shiftreg                                        : std_logic_vector(9 downto 0);
  signal dout                                            : std_logic;
  signal start_bit                                       : std_logic := '0';
  signal stopp_bit                                       : std_logic := '1';
  type tilstand_sender is (s_idle, s_transmit, s_shift_out, s_finish, s_wait);
  signal state_sender                                    : tilstand_sender;
  type tilstand_mottaker is (s_idle, s_wait_for_sender, s_shift_in, s_offload, S_error);
  signal state_mottaker                                  : tilstand_mottaker;
  signal start                                           : std_logic;
  signal data_inn_q, data_inn_qq, data_inn_qqq, data_inn : std_logic;
  signal state_error                                     : std_logic;
  signal mottatt_bit                                     : std_logic;
  signal data_reg                                        : std_logic_vector(7 downto 0);
  signal start_teller, baud_enable_m, baud_enable_s      : std_logic;


begin
  LEDR(17)         <= hallo;
  sender           <= SW(17);
  LEDG(0)          <= sender;
  LEDG(7)          <= mottatt_blink;
  start            <= KEY(0);
  data_inn         <= GPIO(7)        when sender = '0' else '1';
  GPIO(7)          <= dout           when sender = '1' else 'Z';
  GPIO(1)          <= hallo          when sender = '1' else 'Z';
  LEDR(7 downto 0) <= SW(7 downto 0) when sender = '1' else data_reg(7 downto 0);
  LEDR(16)         <= state_error    when sender = '0' else '0';
  p_send_motta_hallo : process (CLOCK_50) is
  begin
    if rising_edge(CLOCK_50) then
      if sender = '1' then
        -- sender
        mottatt_blink <= '0';
        if resetn = '0' then
          GPIO(5)      <= '1';
          state_sender <= s_idle;
        else
          GPIO(5) <= '0';
          case state_sender is
            when s_idle =>
              shiftreg <= (others => '0');
              dout     <= '1';
              if start = '0' then
                state_sender <= s_transmit;
              end if;
            when s_transmit =>
              dout         <= '1';
              shiftreg     <= stopp_bit & SW(8 downto 1) & start_bit;
              state_sender <= s_shift_out;
            when s_shift_out =>
              if baud_enable_s = '1' then
                shiftreg <= '0' & shiftreg(9 downto 1);
                dout     <= shiftreg(0);
              elsif shiftreg = "0000000000" then
                state_sender <= s_finish;
              end if;
            when s_finish =>
              dout         <= '1';
              state_sender <= s_wait;
            when s_wait =>
              state_sender <= s_transmit;
            when others =>
              state_sender <= s_idle;
          end case;
        end if;

      else
        -- mottaker
        GPIO(5) <= 'Z';

        vippe_a       <= GPIO(1);
        vippe_b       <= vippe_a;
        mottatt_blink <= vippe_b;

        if GPIO(5) = '1' then
          state_mottaker <= s_idle;
        else
          case state_mottaker is
            when s_idle =>
              state_error <= '0';
              shiftreg    <= (9 => '1', others => '0');
              if mottatt_bit = '1' then
                state_mottaker <= s_wait_for_sender;
              end if;
            when s_wait_for_sender =>
              if mottatt_bit = '0' then
                state_mottaker <= s_shift_in;
              end if;
            when s_shift_in =>
              if baud_enable_m = '1' then
                shiftreg <= mottatt_bit & shiftreg(9 downto 1);
                if shiftreg(0) = '1' and shiftreg(9) = '0' then
                  state_mottaker <= S_error;
                elsif shiftreg(0) = '1' and shiftreg(9) = '1' then
                  state_mottaker <= s_offload;
                end if;
              end if;
            when S_error =>
              state_error <= '1';
            when s_offload =>
              data_reg(7 downto 0) <= shiftreg(8 downto 1);
              state_mottaker       <= s_idle;
            when others =>
              state_mottaker <= s_idle;
          end case;
        end if;
      end if;
    end if;

  end process;





  p_start_teller : process (CLOCK_50) is
  begin
    if rising_edge(CLOCK_50) then
      if resetn = '0' then
        start_teller <= '0';
        data_inn_q   <= '0';
        data_inn_qq  <= '0';
        data_inn_qqq <= '0';
      else
        start_teller <= '0';
        data_inn_q   <= data_inn;
        data_inn_qq  <= data_inn_q;
        data_inn_qqq <= data_inn_qq;
        if data_inn_qqq = '1' and data_inn_qq = '0' then
          mottatt_bit <= '1';
          if state_mottaker = s_wait_for_sender then
            start_teller <= '1';
          end if;
        end if;
      end if;
    end if;

  end process p_start_teller;


  baudrate_gen_inst : component baudrate_gen
    port map(
      CLOCK_50      => CLOCK_50,
      resetn        => resetn,
      velg_baudrate => SW(16 downto 14),
      start_teller  => start_teller,
      baud_enable_m => baud_enable_m,
      baud_enable_s => baud_enable_s
      );

  Enable_gen_inst : component Enable_gen
    port map(
      clock_50    => CLOCK_50,
      resetn      => resetn,
      velg_enable => "000",
      Enable      => hallo_enable
      );

  reset_synchronizer_inst : component reset_synchronizer
    port map(
      clk        => CLOCK_50,
      reset_key3 => KEY(3),
      reset_clk  => resetn
      );

  p_hallo : process (CLOCK_50) is
  begin
    if rising_edge(CLOCK_50) then
      if resetn = '0' then
        hallo <= '0';
      elsif hallo_enable = '1' then
        hallo <= not hallo;
      end if;
    end if;
  end process p_hallo;



end architecture RTL;