library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_signed.all;
entity Projekt is
port(clk_i: in std_logic := '0';
     rst_i: in std_logic := '0';
     led_o: out std_logic_vector(0 downto 0) := "0");
constant N : integer := 25000000;
end Projekt;

architecture Behavioral of Projekt is
signal temp: integer:=0;
signal output: std_logic:= '0';
begin process(clk_i,rst_i,temp,output)
begin
if ( temp < N - 1) then
    if rst_i='1' then
        temp <= 0;
        led_o(0) <= '0';
    elsif(clk_i'event and clk_i='1') then
        temp <= temp + 1;
    else temp <= temp;
    end if;
else output <= not output;
     temp <= 0;
     led_o(0) <= output;
     end if;
end process;
end Behavioral;