Ideas...

-- FROM ALTERA and INTEL online...

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE WORK.filt_cmp.ALL;

ENTITY cmpl_sig IS
PORT (a, b, sel : IN STD_LOGIC;
    x, y, z : OUT STD_LOGIC);
END ENTITY cmpl_sig;

ARCHITECTURE logic OF cmpl_sig IS
BEGIN
    -- Simple Signal Assign...
    X <= (a AND NOT sel) OR (b AND sel);
    -- Cond. Signal Assign...
    Y <= A WHEN sel='0' ELSE
        B;
    -- Selected Signal Assignment
    Z <= a WHEN '0';
         B WHEN '1';
         '0' WHEN OTHERS;
END ARCHITECTURE logic;