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Mar 21st, 2019
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VHDL 0.48 KB | None | 0 0
  1.  
  2.     SSB: PROCESS(clk_1khz, rst_state)
  3.     variable counter : integer := 0;
  4.     begin
  5.         if(rst_state = '1') then
  6.             counter := 0;
  7.             ssb_state <= 0;
  8.         elsif(rising_edge(clk_1khz)) then
  9.             if(start_stop_button_i = '1') then
  10.                 counter := counter + 1;
  11.             else
  12.                 if(counter > 50) then
  13.                     if(ssb_state = 2) then
  14.                         ssb_state <= 0;
  15.                         ssb_reset <= '1';
  16.                     else
  17.                         ssb_state <= ssb_state + 1;
  18.                     end if;
  19.                 end if;
  20.                 counter := 0;
  21.             end if;
  22.         end if;
  23.    
  24.     end process;
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