ISP Lab 5B

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-- Company:
-- Engineer:
--
-- Create Date:    08:36:32 05/28/2013
-- Design Name:
-- Module Name:    main - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity main is
    Port ( clk_i : in  STD_LOGIC;
           rgb_o : out STD_LOGIC_VECTOR(2 downto 0);
              hsync_o : out STD_LOGIC;
              vsync_o : out STD_LOGIC;
              sw_i : in STD_LOGIC_VECTOR(7 downto 0);
              btn_i : in STD_LOGIC_VECTOR(3 downto 0));
end main;

architecture Structural of main is

component memory
    port (
    clka: IN std_logic;
    dina: IN std_logic_VECTOR(0 downto 0);
    addra: IN std_logic_VECTOR(17 downto 0);
    wea: IN std_logic_VECTOR(0 downto 0);
    clkb: IN std_logic;
    addrb: IN std_logic_VECTOR(17 downto 0);
    doutb: OUT std_logic_VECTOR(0 downto 0));
end component;

component sinus IS
   PORT (
      DATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
      WE : IN STD_LOGIC;
      A : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
      CLK : IN STD_LOGIC;
      SCLR : IN STD_LOGIC;
      CHANNEL : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
      RDY : OUT STD_LOGIC;
      SINE : OUT STD_LOGIC_VECTOR(10 DOWNTO 0)
);
END component;

component VGAsync is
     Port ( clk_i : in STD_LOGIC;
                hsync_o : out STD_LOGIC;
                vsync_o : out STD_LOGIC;
                pixelX : out integer range 640 downto 0;
                pixelY : out integer range 480 downto 0);
end component;

signal lowClk : std_logic := '0';

signal addrW : std_logic_vector(17 downto 0);
signal addrR : std_logic_vector(17 downto 0);
signal x : std_logic;
signal y : std_logic;
signal memRead : std_logic_vector(0 downto 0);
signal memWrite : std_logic_vector(0 downto 0);
signal writeEnable : std_logic_vector(0 downto 0);
signal pixelX : integer range 640 downto 0;
signal pixelY : integer range 480 downto 0;
signal pixAddr : integer range 147456 downto 0;

signal singenData : std_logic_vector(15 downto 0);
signal addrSel : std_logic_vector(4 downto 0);
signal wrEnable : std_logic := '0';
signal resetGen : std_logic := '0';

signal channel : std_logic_vector(0 downto 0);
signal genRdy : std_logic;
signal sinOut : std_logic_vector(10 downto 0);

constant PIXEL : std_logic_vector(2 downto 0) := "111";
constant BACKGROUND : std_logic_vector(2 downto 0) := "000";

signal Xoffset : integer range 640 downto 0 := 128;
signal Yoffset : integer range 480 downto 0 := 48;

signal clearScr : std_logic := '1';

signal rstBtn : std_logic := '0'; --nowa zmienna

begin

videoMem : memory port map(
    clka => clk_i,
    dina => memWrite,
    addra => addrW,
    wea => writeEnable,
    clkb => clk_i,
    addrb => addrR,
    doutb => memRead );

generator : sinus PORT map(
      DATA => singenData,   -- data input to the gen.
      WE => wrEnable, -- write enable - read from DATA into registers PINC or POFF
      A => addrSel, -- address select for DATA to write to when WE
        -- 00000 to 01111 phase increment for ch. 0 through 15 (PINC)
        -- 10000 to 11111 phase offset for ch. 0 through 15 (POFF)
      CLK => clk_i, -- clock
      SCLR => resetGen, -- synchronous clear
      CHANNEL => channel, -- shows which channel is currently displayed
      RDY => genRdy, -- indicates that the data is ready to read
      SINE => sinOut -- output sinus data
);

pushButtons : process(clk_i)
begin
    if rising_edge(clk_i) then -- ponizej buttony maja byc porownywane do 1 a nie do 0
        if btn_i(0)='1' then
            singenData(15 downto 0) <= "00000000"&sw_i;
            addrSel <= "00000";
            wrEnable <= '1';
        elsif btn_i(1)='1' then
            singenData(`5 downto 0) <= "00000000"&sw_i;
            addrSel <= "00001";
            wrEnable <= '1';
        elsif btn_i(2)='1' then
            singenData(15 downto 0) <= sw_i&"00000000";
            addrSel <= "10000";
            wrEnable <= '1';
        else
            wrEnable <= '0';
        end if;
    end if;
end process;

writeRGB : process(pixelX, pixelY)
    variable tmpXoffset : integer range 640 downto 0 := 0;
    variable tmpYoffset : integer range 480 downto 0 := 0;
begin
    tmpXoffset := Xoffset + 12;
    tmpYoffset := Yoffset + 7;

    if (pixelX >= tmpXoffset) and (pixelY >= tmpYoffset) and (pixelX < tmpXoffset + 384) then
        pixAddr <= (pixelX-tmpXoffset) + ((pixelY-tmpYoffset)*384); -- a tutaj +2
        addrR <= std_logic_vector(to_unsigned(pixAddr, 18));
        if memRead(0)='1' then
            rgb_o <= PIXEL;
        else
            rgb_o <= BACKGROUND;
        end if;
    else
        rgb_o <= BACKGROUND;
    end if;
end process;

setMemory : process (clk_i)
    variable Xmemory : integer range 386 downto 0 := 386;
    variable Ymemory : integer range 386 downto 0 := 386;
    variable wrtAddr : integer range 147456 downto 0 := 0;
begin
    if rising_edge(clk_i) then
        if btn_i(3)='1' then --nowy if do wyeliminowania wyscigow na buttonie 3
            rstBtn <= '1'
        end if;
        if rstBtn = '1' then
            Xmemory := 0;
            Ymemory := 0;
            clearScr <= '1';
            resetGen <= '1';
            rstBtn <= '0';
        elsif clearScr='1' then
            if resetGen='1' then
                resetGen <= '0';
            end if;
            if lowClk='1' then
                writeEnable(0) <= '0';
            elsif Xmemory<385 and Ymemory<385 then
                wrtAddr := (Xmemory) + ((Ymemory)*384);
                memWrite(0) <= '0';
                addrW <= std_logic_vector(to_unsigned(wrtAddr, 18));
                writeEnable(0) <= '1';
                Xmemory := Xmemory + 1;
                if Xmemory=385 then
                    Ymemory := Ymemory + 1;
                    Xmemory := 0;
                end if;
            elsif Ymemory=385 then
                clearScr <= '0';
            end if;
        else
            if writeEnable(0)='1' then
                writeEnable(0) <= '0';
            end if;
            if genRdy='1' then
                if channel(0)='0' then
                    Xmemory := conv_integer(sinOut)*3/16 + 192;
                else
                    Ymemory := conv_integer(sinOut)*3/16 + 192;
                    wrtAddr := (Xmemory) + ((Ymemory)*384);
                    memWrite(0) <= '1';
                    addrW <= std_logic_vector(to_unsigned(wrtAddr, 18));
                    writeEnable(0) <= '1';
                end if;
            end if;
        end if;
    end if;
end process;

monitor_sync : VGAsync port map(
    clk_i => lowClk,
    hsync_o => hsync_o,
    vsync_o => vsync_o,
    pixelX => pixelX,
    pixelY => pixelY );

clockDivider : process(clk_i)
begin
    if rising_edge(clk_i) then
        if lowClk='0' then
            lowClk <= '1';
        else
            lowClk <= '0';
        end if;
    end if;
end process;

end Structural;