lab6code

-- CPU_2214 TESTBENCH
library ieee;
use ieee.std_logic_1164.all;


entity CPU_2214_Test is
end entity CPU_2214_Test;


architecture mixed of CPU_2214_Test is
    constant tick : time := 100 ns;
    signal reset, clock : std_logic;
    signal instruction : std_logic_vector(0 to 15);
     signal sout : std_logic_vector(15 downto 0);
begin
    CPU_2214_Sim : entity work.CPU_2214
        port map(
            clk     => clock,
            clear   => reset,
            instruction => instruction,
                sout => sout
        );

    driver : process is
    begin
        -- reset the system
        reset <= '0'; instruction <= x"0000"; wait for 50 ns;
        reset <= '1';

        -- ADD r2, r1, r1
        instruction <= x"0211"; wait for tick;

        -- ADDI r3, r2, 5
        instruction <= x"4325"; wait for tick;

        -- SUB r4, r3, r2
        instruction <= x"1432"; wait for tick;

        -- SUBI r5, r4, -4
        instruction <= x"5544"; wait for tick;

        -- AND r6, r3, r5
        instruction <= x"2635"; wait for tick;

        -- OR r7, r5, r4
        instruction <= x"3754"; wait for tick;

        wait;
    end process driver;

    clock_p : process is
    begin
        for i in 0 to 18 loop
            clock <= '1'; wait for tick/2;
            clock <= '0'; wait for tick/2;
        end loop;
        wait;
    end process clock_p;
end architecture mixed;
---------------------------------------------------------------------------------------------------------------------------------------
-- SIGN EXTEND
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

Entity Signextend is
    port(
        immIn           :   in      std_logic_vector( 3 downto 0);
        immOut      :   out std_logic_vector(15 downto 0)
        );
End Signextend;

architecture syn of Signextend is

begin
    immOut(0)   <=  immIn(0);
    immOut(1)   <=  immIn(1);
    immOut(2)   <=  immIn(2);
    immOut(3)   <=  immIn(3);
    immOut(4)   <=  immIn(3);
    immOut(5)   <=  immIn(3);
    immOut(6)   <=  immIn(3);
    immOut(7)   <=  immIn(3);
    immOut(8)   <=  immIn(3);
    immOut(9)   <=  immIn(3);
    immOut(10)  <=  immIn(3);
    immOut(11)  <=  immIn(3);
    immOut(12)  <=  immIn(3);
    immOut(13)  <=  immIn(3);
    immOut(14)  <=  immIn(3);
    immOut(15)  <=  immIn(3);
end syn;
---------------------------------------------------------------------------------------------------------------------------------------
-- CONTROL
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

Entity Control is
    port(
        op          :   in  std_logic_vector( 3 downto 0);
        alu_op      :   out std_logic_vector( 1 downto 0);
        alu_src     :   out std_logic
        );
End Control;

architecture syn of Control is

begin
    process (op) is
    begin
        case op is

            -- op=0, ADD
            when x"0" =>
                alu_op      <=  "00";
                alu_src     <=  '0';

            -- op=1, SUB
            when x"1" =>
                alu_op      <=  "01";
                alu_src     <=  '0';


            -- op=2, AND
            when x"2" =>
                alu_op      <= "10";
                alu_src     <= '0';

            -- op=3, OR
            when x"3" =>
                alu_op      <=  "11";
                alu_src     <= '0';


            -- op=4, ADDi
            when x"4" =>
                alu_op      <= "00";
                alu_src     <= '1';


            -- op=5, SUBi
            when x"5" =>
                alu_op      <= "01";
                alu_src     <= '1';

            -- op=8, LW
            -- Not for this lab

            -- op=C, SW
            -- Not for this lab

            -- op=7, SLT
            -- Not for this lab

            when others =>
                alu_op  <=  "00";
                alu_src <=  '0';

        end case;
    end process;
end syn;
---------------------------------------------------------------------------------------------------------------------------------------
-- CPU 2214 MODULE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;


entity CPU_2214 is
    port(
        clk : in std_logic;
        clear : in std_logic;
        instruction : in std_logic_vector(15 downto 0);
        sout       : out std_logic_vector(15 downto 0)
    );
end CPU_2214;

architecture Behavioral of CPU_2214 is
    COMPONENT ALU_16Bit
        port(
        A       :   in      std_logic_vector(15 downto 0);
        B       :   in      std_logic_vector(15 downto 0);
        S       :   in      std_logic_vector(1 downto 0);
        Sout    :   out     std_logic_vector(15 downto 0);
        Cout    :   out std_logic
        );
    END COMPONENT;

    COMPONENT Registers
        port(
        clk :   in   std_logic;
        clear   :   in  std_logic;

        a_addr: in   std_logic_vector( 3 downto 0);
        a_data: in   std_logic_vector(15 downto 0);
        load    :   in   std_logic;

        b_addr: in   std_logic_vector( 3 downto 0);
        c_addr: in   std_logic_vector( 3 downto 0);

        b_data: out std_logic_vector(15 downto 0);
        c_data: out std_logic_vector(15 downto 0)
        );
    END COMPONENT;

    COMPONENT Control
        port(
        op              :   in  std_logic_vector( 3 downto 0);
        alu_op      :   out std_logic_vector( 1 downto 0);
        alu_src     :   out std_logic
        );
    end component;

    component Signextend
        port(
        immIn           :   in  std_logic_vector( 3 downto 0);
        immOut      :   out std_logic_vector(15 downto 0)
        );
    end component;

    component mux2_1
   generic (WIDTH : positive:=16);
    port(
        Input1      :   in      std_logic_vector(WIDTH-1    downto 0);
        Input2      :   in      std_logic_vector(WIDTH-1    downto 0);
        S               :   in      std_logic;
        Sout            :   out std_logic_vector(WIDTH-1    downto 0));
    end component;

    -- Signals
    signal  op                      :   std_logic_vector( 3 downto 0)   ;
    signal  rd                      :   std_logic_vector( 3 downto 0)   ;
    signal  rs                      :   std_logic_vector( 3 downto 0)   ;
    signal  rt                      :   std_logic_vector( 3 downto 0)   ;
    signal  sout_alu                :   std_logic_vector(15 downto 0)   ;
    signal  cout                    :   std_logic                           ;
    signal  rs_data             :   std_logic_vector(15 downto 0)   ;
    signal  rt_data             :   std_logic_vector(15 downto 0)   ;
    signal ctrl_alu_op    : std_logic_vector(1 downto 0);
    signal ctrl_alu_src   : std_logic;
    signal sign_out       : std_logic_vector(15 downto 0);
    signal mux_out        : std_logic_vector(15 downto 0);

    -- more signals

begin
    --------------------------------------------------------------------------
    -- Instruction Fetch
    --------------------------------------------------------------------------
    op      <=  instruction(15 downto 12);
    rd      <= instruction(11 downto  8);
    rs      <= instruction(7  downto  4);
    rt      <= instruction(3  downto  0);
    --------------------------------------------------------------------------
    -- Instruction Decode
    --------------------------------------------------------------------------
    CPU_Control_0:          Control port map(
        op          =>  op,
        alu_op  =>  ctrl_alu_op,
        alu_src =>  ctrl_alu_src
    );

    CPU_Registers_0:        Registers port map(
        clk     =>  clk,
        clear       =>  clear,

        a_addr  =>  rd,
        a_data  =>  sout_alu,
        load        =>  '1',

        b_addr  =>  rs,
        c_addr  =>  rt,

        b_data  =>  rs_data,
        c_data  =>  rt_data
    );

    CPU_signextend_0:       Signextend port map(
        immIn       =>  rt,
        immOut  =>  sign_out
    );

    --------------------------------------------------------------------------
    -- Execute
    --------------------------------------------------------------------------
    CPU_alu_src_mux:        mux2_1 generic map(16) port map(
        Input1  => rt_data,
        Input2  =>  sign_out,
        S           =>  ctrl_alu_src,
        Sout        =>  mux_out
    );

    CPU_ALU_0:              ALU_16Bit port map(
        A           =>  rs_data,
        B           =>  mux_out,
        S           =>  ctrl_alu_op,
        Sout        =>  sout_alu,
        Cout        =>  cout
    );

    sout <= sout_alu;

    --------------------------------------------------------------------------
    -- Memory
    --------------------------------------------------------------------------

    -- Not for this lab

    --------------------------------------------------------------------------
    -- Write Back
    --------------------------------------------------------------------------

    -- Not for this lab

end Behavioral;