library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

ENTITY part1 is
Port(clk,RD: IN std_logic;
      addr: IN std_logic_vector(1 downto 0);
      data_out: out std_logic_vector(7 downto 0));
end;

ARCHITECTURE arch of part1 is
Type rom_array is array (0 to 3) of std_logic_vector(7 downto 0);
constant rom: rom_array := (x"C0",
                                     x"D1",
                                     x"E2",
                                     x"F3");
Begin
    Process(clk, addr)
        Begin
            if (clk' event and clk ='0') then
                if (RD = '1') then
                Data_out <= rom (to_integer( unsigned(addr)));
                elsif (RD = '0') then Data_out <= "ZZZZZZZZ";
            end if; end if;
        end process;
end arch;