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- library IEEE;
- use IEEE.std_logic_1164.all; -- biblioteca do IEEE
- entity ontoin1703 is port -- a entidade deve ter o mesmo nome do projeto criado
- (
- D : in std_logic; -- entrada digital A
- clk : in std_logic; -- entrada digital B
- Q : out std_logic; -- entrada digital C
- Qn : out std_logic -- saida digital O
- );
- end ontoin1703;
- architecture hardware of ontoin1703 is -- eh descricao do circuito que nesse caso eh a porta 1
- signal dado : std_logic;
- begin -- inicia a descricao do programa
- dado <= D when (clk = '1') else dado;
- Q <= dado;
- Qn <= dado;
- end hardware; -- final da implementacao
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