MODULO

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity modulo is
    Port ( e : in  STD_LOGIC;
           a : in  STD_LOGIC;
           b : in  STD_LOGIC;
           w : in  STD_LOGIC;
           y0 : out  STD_LOGIC;
           y1 : out  STD_LOGIC;
           y2 : out  STD_LOGIC;
           y3 : out  STD_LOGIC);
end modulo;

architecture Behavioral of modulo is

begin

process(w, a, b, e) is

begin

        y0 <= '0';
        y1 <= '0';
        y2 <= '0';
        y3 <= '0';
    if(e = '1')then

        if(a = '0' and b = '0')then
            y0 <= w;
        elsif(a = '0' and b = '1')then
            y1 <= w;
        elsif(a = '1' and b = '0')then
            y2 <= w;
        elsif(a = '1' and b = '1')then
            y3 <= w;
        end if;
    end if;
end process;

end Behavioral;