library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity SigGenControl is
  port( reset, sCLK, mCLK, FreqBTN, AmplBTN, ShapeBTN: in std_logic;
        MOSI, SS: in std_logic;
          MISO, SigEn : out std_logic;
        Shape  : inout std_logic_vector(2 downto 0);
        Ampl   : inout std_logic_vector(7 downto 0);
          DataOut: inout std_logic_vector(19 downto 0);
        Freq   : inout std_logic_vector(7 downto 0));
end SigGenControl;

architecture Behavioral of SigGenControl is

signal DataStreamInternal, DatastreamInternalSync: std_logic_vector(39 downto 0);
signal StartByte, AckByte, AckByteLoaded, CalcChecksum, FreqInternal, AmplInternal: std_logic_vector(7 downto 0);
signal SetEnable: std_logic;
signal ShapeInternal: std_logic_vector(2 downto 0);
signal DataOutInternal: std_logic_vector(19 downto 0);

type StateType is (FreqS, AmplS, ShapeS, ResS);
signal State, NextState: StateType;

begin

StartByte <= "01010101";    -- X"55"
AckByte <= "10011001";      -- X"99"

CalcChecksum <= DatastreamInternalsync(39 downto 32) xor DatastreamInternalsync(31 downto 24) xor DatastreamInternalsync(23 downto 16) xor DatastreamInternalsync(15 downto 8) xor DatastreamInternalsync(7 downto 0);

SigEN <= '1';

----------------------------------------------------------------MOSIReg-------------------------------------------------------------
MOSIReg: process(reset, sCLK, SS)
    begin
        if reset = '1' then
            DataStreamInternal <= X"0000000000";

        elsif SS = '0' then
            if sClk'event and sClk = '1' then
                DatastreamInternal <= DatastreamInternal(38 downto 0) & MOSI;
            else
                DatastreamInternal <= DatastreamInternal;
            end if;
        end if;


end process;

----------------------------------------------------------------MISOReg-------------------------------------------------------------
MISOReg: process(reset, sCLK, SetEnable, AckByteLoaded)
    begin
        if reset = '1' then
                AckByteLoaded <= X"00";

        elsif sCLK'event and sCLK = '0' then
            if SetEnable = '1' then
                AckByteLoaded <= AckByte;
            else
                AckByteLoaded <= AckByteLoaded(6 downto 0) & '0';
            end if;
        end if;

        MISO <= AckByteLoaded(7);

end process;
----------------------------------------------------------------SyncReg-------------------------------------------------------------
SyncReg: process(Reset, mClk)
begin
  if Reset='1' then DatastreamInternalsync <= X"0000000000";

  elsif mClk'event and mClk = '1' then
        DatastreamInternalsync <= DatastreamInternal;
  end if;
end process;


----------------------------------------------------------------StateReg-------------------------------------------------------------

StateReg: process (reset, mClk)
begin
  if reset = '1' then State <= ResS;

  elsif mClk'event and mClk = '1' then
        State <= NextState;
    end if;
end process;

----------------------------------------------------------------DispReg--------------------------------------------------------------
StateDec: process (State, Reset, Reset, FreqBTN, AmplBTN, ShapeBTN, Freq, Ampl, Shape)
begin
    case State is
        when FreqS =>
                    DataOutInternal(19 downto 16) <= X"0";

                    DataOutInternal(3 downto 0) <= X"F";
                    DataOutInternal(7 downto 4) <= X"0";
                    DataOutInternal(11 downto 8) <= Freq(7 downto 4);
                    DataOutInternal(15 downto 12) <= Freq(3 downto 0);

               if Reset = '1' then
               NextState <= ResS;
               elsif FreqBTN = '1' then
               NextState <= FreqS;
               elsif AmplBTN = '1' then
               NextState <= AmplS;
               elsif ShapeBTN = '1' then
               NextState <= ShapeS;
                else
                    NextState <= State;
            end if;
-------------------------------------------------------------------
        when AmplS =>
                    DataOutInternal(19 downto 16) <= X"0";

                    DataOutInternal(3 downto 0) <= X"A";
                    DataOutInternal(7 downto 4) <= X"0";
                    DataOutInternal(11 downto 8) <= Ampl(7 downto 4);
                    DataOutInternal(15 downto 12) <= Ampl(3 downto 0);

               if Reset = '1' then
               NextState <= ResS;
               elsif AmplBTN = '1' then
               NextState <= AmplS;
               elsif FreqBTN = '1' then
               NextState <= FreqS;
               elsif ShapeBTN = '1' then
               NextState <= ShapeS;
                else
                    NextState <= State;
            end if;
-------------------------------------------------------------------
        when ShapeS =>
                    DataOutInternal(19 downto 16) <= X"0";

                    DataOutInternal(3 downto 0) <= X"5";
                    DataOutInternal(7 downto 4) <= X"0";
                    DataOutInternal(11 downto 8) <= X"0";
                    DataOutInternal(15 downto 12) <= "0" & Shape;

               if Reset = '1' then
               NextState <= ResS;
               elsif FreqBTN = '1' then
               NextState <= FreqS;
               elsif AmplBTN = '1' then
               NextState <= AmplS;
               elsif ShapeBTN = '1' then
               NextState <= ShapeS;
                else
                    NextState <= State;
            end if;
-------------------------------------------------------------------
        when ResS =>
                DataOutInternal <= X"f05e1"; --skriv "res" med alternativ databank

               if FreqBTN = '1' then
               NextState <= FreqS;
               elsif AmplBTN = '1' then
               NextState <= AmplS;
               elsif ShapeBTN = '1' then
               NextState <= ShapeS;
               elsif Reset = '1' then
               NextState <= ResS;
                else
                    NextState <= State;
            end if;
-------------------------------------------------------------------
        when others =>
            NextState <= State;
-------------------------------------------------------------------
    end case;

     DataOut <= DataOutInternal;

end process;

----------------------------------------------------------------Checksum-------------------------------------------------------------
ChecksumDec: process (DatastreamInternalSync, CalcCheckSum, StartByte, mClk, Reset)
begin

        if (DatastreamInternalSync(39 downto 32) = StartByte) and (CalcCheckSum = X"00") then
            SetEnable <= '1';
        else
            SetEnable <= '0';
        end if;

    end process;

----------------------------------------------------------------Frekvens-------------------------------------------------------------
FreqReg: process (reset, mCLK, FreqInternal, ShapeBTN, DatastreamInternalSync)
begin
    if reset = '1' then
            FreqInternal <= X"00";
            Freq <= X"00";

    elsif mCLK'event and mCLK = '1' then
        if SetEnable = '1' then
            FreqInternal <= DatastreamInternalSync(31 downto 24);
        else
            FreqInternal <= FreqInternal;
        end if;
    end if;

    Freq <= FreqInternal;
end process;

----------------------------------------------------------------Amplitude-------------------------------------------------------------
AmplitudeReg: process (reset, mCLK, AmplInternal, DatastreamInternalSync)
begin
    if reset = '1' then
            AmplInternal <= X"00";
            Ampl <= X"00";

    elsif mCLK'event and mCLK = '1' then
        if SetEnable = '1' then
            AmplInternal <= DatastreamInternalSync(23 downto 16);
        else
            AmplInternal <= AmplInternal;
        end if;
    end if;

    Ampl <= AmplInternal;
end process;

----------------------------------------------------------------Shape-------------------------------------------------------------
ShapeReg: process (reset, mCLK, ShapeInternal, DatastreamInternalSync)
begin
    if reset = '1' then
            ShapeInternal <= "000";

    elsif mCLK'event and mCLK = '1' then
        if SetEnable = '1' then
            ShapeInternal <= DatastreamInternalSync(10 downto 8);
        else
            ShapeInternal <= ShapeInternal;
        end if;
    end if;

    Shape <= ShapeInternal;
end process;
end Behavioral;