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intricate_potato

abdullah39_q1

Jan 7th, 2021
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VHDL 0.26 KB | None | 0 0
  1. --180041239
  2. if(rising_edge(clock))t
  3.    if(AB = x"FF" and IAB = '0') then        
  4.          -- check whether A = B and IAB =0 or not
  5.             Result <= '0';
  6.     else
  7.      Result <= '1';
  8.     end if;
  9.  end if;
  10.  end process;
  11.  Output <= Result;
  12. end Behavioral;
  13.  
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