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-- Company:
-- Engineer:
--
-- Create Date:    20:37:43 01/14/2019
-- Design Name:
-- Module Name:    test - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity test is
    Port ( CLK_50MHz : in  STD_LOGIC;
           RGB : in  STD_LOGIC_VECTOR (2 downto 0);
           VGA_R : out  STD_LOGIC;
           VGA_G : out  STD_LOGIC;
           VGA_B : out  STD_LOGIC;
           VGA_HS : out  STD_LOGIC;
           VGA_VS : out  STD_LOGIC;
           PIX_X : out  STD_LOGIC_VECTOR (9 downto 0);
           PIX_Y : out  STD_LOGIC_VECTOR (8 downto 0));
end test;

architecture Behavioral of test is
    signal CLK_25MHz: STD_LOGIC  := '0';
   signal counter : integer range 0 to 255 := 0;
    signal h_cnt : integer range 0 to 799 := 0;
    signal v_cnt : integer range 0 to 520 := 0;
begin

clk_div :process(CLK_50MHz)
    begin
        if rising_edge(CLK_50MHz) then
            if (counter = 1) then
            CLK_25MHz <= NOT(CLK_25MHz);
            counter <= 0;
         else
                counter <= counter + 1;
            end if;
        end if;
    end process;

counters :process(CLK_25MHz)
    begin
        if rising_edge(CLK_25MHz) then
            if (h_cnt = 799) then
                VGA_HS <= '0'; -- back to start of line
            h_cnt <= 0;
                v_cnt <= v_cnt + 1;

                if (v_cnt = 520) then
                    VGA_VS <= '0'; -- back to start of monitor
                    v_cnt <= 0;
                end if;
            else
                h_cnt <= h_cnt + 1;
                VGA_HS <= '1'; -- keep signal up
                VGA_VS <= '1'; -- keep signal up
            end if;
        end if;
    end process;

color :process(h_cnt, v_cnt, RGB)
    begin
        if h_cnt < 639 and v_cnt < 479 then
            VGA_R <= RGB(0);
            VGA_G <= RGB(1);
            VGA_B <= RGB(2);
        else
            VGA_R <= '0';
            VGA_G <= '0';
            VGA_B <= '0';
        end if;
    end process;

    PIX_X <= std_logic_vector(to_unsigned(myStr( conv_integer(h_cnt)),8));
   PIX_Y <= std_logic_vector(to_unsigned(myStr( conv_integer(v_cnt)),8));

end Behavioral;