----------------------------------------------------------------------------------
-- Company:
-- Engineer: Frans Schreuder
--
-- Create Date: 08/04/2015 08:21:34 AM
-- Design Name:
-- Module Name: FT232H_interface - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
-- Copyright (C) 2015  Frans Schreuder
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program.  If not, see <http://www.gnu.org/licenses/>.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
library UNISIM;
use UNISIM.VComponents.all;

entity FT232H_interface is
  Port (
      FT232_DATA         : inout  std_logic_vector(7 downto 0);
      FT232_RXF          : in     std_logic;
      FT232_TXE          : in     std_logic;
      FT232_RD           : out    std_logic;
      FT232_WR           : out    std_logic;
      FT232_CLKOUT       : in     std_logic;
      FT232_OE           : out    std_logic;
      FT232_SIWU         : out    std_logic;
      FT232_PWRSAV       : out    std_logic;

      fifo_clk           : in     std_logic;
      reset              : in     std_logic;
      rxfifo_dout        : out    std_logic_vector(7 downto 0);
      rxfifo_empty       : out    std_logic;
      rxfifo_rden        : in     std_logic;

      txfifo_din         : in     std_logic_vector(7 downto 0);
      txfifo_full        : out    std_logic;
      txfifo_wren        : in     std_logic

  );
end FT232H_interface;

architecture Behavioral of FT232H_interface is

COMPONENT fifo_128x8
  PORT (
    rst : IN STD_LOGIC;
    wr_clk : IN STD_LOGIC;
    rd_clk : IN STD_LOGIC;
    din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
    wr_en : IN STD_LOGIC;
    rd_en : IN STD_LOGIC;
    dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
    full : OUT STD_LOGIC;
    empty : OUT STD_LOGIC;
    almost_full : OUT STD_LOGIC
  );
END COMPONENT;

  signal txfifo_dout : std_logic_vector(7 downto 0);
  signal txfifo_rden : std_logic;
  signal txfifo_empty : std_logic;
  signal rxfifo_din  : std_logic_vector(7 downto 0);
  signal rxfifo_wren : std_logic;
  signal rxfifo_full : std_logic;

  signal databuf_T : std_logic;

  signal clkout : std_logic;
  signal FT232_OE_s: std_logic;
  signal FT232_OE_p1: std_logic;
  signal FT232_OE_p2: std_logic;
  signal FT232_RD_s: std_logic;
begin
 FT232_SIWU <= '1';
 FT232_PWRSAV <= '1';

clkout_bufg: BUFG
 port map(
    I => FT232_CLKOUT,
    O => clkout);

txfifo: fifo_128x8
  PORT MAP (
    rst => reset,
    wr_clk => fifo_clk,
    rd_clk => clkout,
    din => txfifo_din,
    wr_en => txfifo_wren,
    rd_en => txfifo_rden,
    dout => txfifo_dout,
    full => txfifo_full,
    empty => txfifo_empty
  );

rxfifo: fifo_128x8
  PORT MAP (
    rst => reset,
    wr_clk => clkout,
    rd_clk => fifo_clk,
    din => rxfifo_din,
    wr_en => rxfifo_wren,
    rd_en => rxfifo_rden,
    dout => rxfifo_dout,
    full => open,
    empty => rxfifo_empty,
    almost_full => rxfifo_full
  );


databuf_gen: for i in 0 to 7 generate
    databuf : IOBUF
    generic map (
        DRIVE => 12,
        IOSTANDARD => "DEFAULT",
        SLEW => "FAST")
    port map (
        O => rxfifo_din(i), -- Buffer output
        IO => FT232_DATA(i),-- Buffer inout port (connect directly to top-level port)
        I => txfifo_dout(i),-- Buffer input
        T => databuf_T-- 3-state enable input, high=input, low=output
    );
end generate;

FT232_OE <= FT232_OE_s;
FT232_RD <= FT232_RD_s;

rxfifo_wren <= (not FT232_RD_s) and (not FT232_RXF);

receve: process(clkout)
begin
    if(rising_edge(clkout)) then
        FT232_OE_p1 <= FT232_OE_s;
        FT232_OE_p2 <= FT232_OE_p1;
        FT232_RD_s <= '1';
        FT232_OE_s <= '1';

        if(FT232_RXF = '0' and txfifo_rden = '0') then --not reading from TXfifo and data available in FT232
            FT232_OE_s <= '0';
            if(FT232_OE_s = '0') then --one clock after OE goes low
                if(rxfifo_full = '0') then
                    FT232_RD_s <= '0';
                end if;
            end if;
        end if;
    end if;
end process;


transmit: process( FT232_TXE, FT232_OE_s, FT232_OE_p1, FT232_OE_p2, txfifo_empty)
begin
    txfifo_rden <= '0';
    if(FT232_OE_s = '1' and FT232_OE_p1 = '1' and FT232_OE_p2 = '1') then --make sure that we tristate whenever output is enabled, or 2 clocks after.
        if(FT232_TXE = '0') then
            if(txfifo_empty = '0') then
                txfifo_rden <= '1';
            end if;
        end if;
    end if;
end process;

transmit_c: process(clkout)
begin
    if(rising_edge(clkout)) then
        FT232_WR <= '1';
        databuf_T <= '1';
        if( txfifo_rden = '1') then
            FT232_WR <= '0';
            databuf_T <= '0';
        end if;
    end if;
end process;

end Behavioral;