library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.all;


entity nand_8 is
port (din : in std_logic_vector(7 downto 0);
oddp: out std_logic
);
end;


architecture struct of nand_8 is
begin
 po: process (din)
 variable odd : std_logic;
 begin
 odd := '0';
 for index in 7 downto 0 loop
odd := odd xor din(index);
 end loop;
 oddp <= odd;
 end process;
end struct;