entity ALU is
Port (
    clk : in  STD_LOGIC;
    reset : in  STD_LOGIC;
    operand1: in STD_LOGIC_VECTOR(9 downto 0);
    operand2: in STD_LOGIC_VECTOR(9 downto 0);
    opcode: in STD_LOGIC_VECTOR(4 downto 0);
    result: out STD_LOGIC_VECTOR(9 downto 0);
    status: out STD_LOGIC_VECTOR(1 downto 0));
end ALU;

architecture Behavioral of ALU is
signal saida: STD_LOGIC_VECTOR(9 downto 0) := "0000000000";
signal temp_sum: signed(9 downto 0) := "0000000000";
signal saida_status: STD_LOGIC_VECTOR(1 downto 0):= "00";
begin

    result <= saida when reset = '0' else "0000000000";
    status <= saida_status when reset = '0' else "00";
    saida <=    std_logic_vector(temp_sum);

    --status = 01 quando saida eh 0
    --status = 11 quando saida eh negativa
    saida_status <= "01" when saida = "0000000000" else
                         "11" when saida(9) = '1'         else
                         "00";

    operacao: process(clk, opcode)
    begin
        if rising_edge(clk) then
            if opcode = "00101" then --00101 = OPcode de soma
                temp_sum <= signed(operand1) + signed(operand2);
            elsif opcode = "00110" then --00110 = OPcode de subtracao
                temp_sum <= signed(operand1) - signed(operand2);
            elsif opcode = "00111" then --00111 = OPcode de and logico
                temp_sum <= signed(operand1) and signed(operand2);
            elsif opcode = "01000" then --01000 = OPcode de or logico
                temp_sum <= signed(operand1) or signed(operand2);
            elsif opcode = "01001" then --01001 = OPcode de xor logico
                temp_sum <= signed(operand1) xor signed(operand2);
            elsif opcode = "01010" then --01010  = OPcode de not logico
                temp_sum <= not signed(operand1);
            elsif opcode = "01011" then --01011  = OPcode de nand logico
                temp_sum <= signed(operand1) nand signed(operand2);
            end if;
        end if;
    end process operacao;


end Behavioral;