library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity brojilo4_u_d is
port(
        cp, rst, ud: in std_logic;
        broj: out std_logic_vector (3 downto 0)
);
end brojilo4_u_d;

architecture Opisni of brojilo4_u_d is

    signal temp: std_logic_vector (3 downto 0);
    signal cp_o: std_logic;

begin

S1: entity djeljitelj_frek port map (cp, cp_o);

process(cp_o, rst)
begin

if (rst='1') then
    temp<="0000";
elsif (cp_o'event and cp_o='1') then
    if (ud='1') then
        temp<=temp+1;
    else
        temp<=temp-1;
    end if;
end if;

end process;

broj<=temp;

end Opisni;