Lindenis V5 (Allwinner V5) DRAM MBUS priority

MBUS_CONF(   CPU,  true, HIGHEST, 0,  400,  300,  250);
MBUS_CONF(  MAHB,  true, HIGHEST, 0,  512,  256,   96);
MBUS_CONF(   DMA,  true,    HIGH, 0,  256,  100,   80);
MBUS_CONF(    VE,  true,    HIGH, 2, 8192, 2400, 2200);
MBUS_CONF(  CSI0,  true, HIGHEST, 0, 4096, 2048, 1024);
MBUS_CONF(PORT12,  true,    HIGH, 2, 8192, 1500, 1300);
MBUS_CONF(   VE2,  true,    HIGH, 2,  600,  500,  400);
MBUS_CONF(PORT27,  true,    HIGH, 2, 1500, 1200, 1000);
MBUS_CONF(PORT35,  true,    HIGH, 2, 8192, 1500, 1000);