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Randune1

ProgCnt

Jan 12th, 2023 (edited)
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VHDL 0.29 KB | Source Code | 0 0
  1. entity ProgCnt is
  2.     Port ( Clk : in  STD_LOGIC;
  3.            New_PC : in  STD_LOGIC_VECTOR (5 downto 0);
  4.            PC : out  STD_LOGIC_VECTOR (5 downto 0):= "000000"
  5.               );
  6. end ProgCnt;
  7.  
  8. architecture Behavioral of ProgCnt is
  9.  
  10. begin
  11.     PC <= New_PC when rising_edge(Clk);
  12.  
  13. end Behavioral;
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