Advertisement
Guest User

Untitled

a guest
Mar 21st, 2018
90
0
Never
Not a member of Pastebin yet? Sign Up, it unlocks many cool features!
VHDL 2.29 KB | None | 0 0
  1. library ieee;
  2. use ieee.std_logic_1164.all;
  3. use ieee.numeric_std.all;
  4.  
  5. entity gray_counter is
  6.  
  7.     port
  8.     (
  9.         clk        : in std_logic;
  10.         reset      : in std_logic;
  11.         enable     : in std_logic;
  12.         gray_count : out std_logic_vector(7 downto 0)
  13.     );
  14.    
  15. end entity;
  16.  
  17. -- Implementation:
  18.  
  19. -- There is an imaginary bit in the counter, at q(0), that resets to 1
  20. -- (unlike the rest of the bits of the counter) and flips every clock cycle.
  21. -- The decision of whether to flip any non-imaginary bit in the counter
  22. -- depends solely on the bits below it, down to the imaginary bit.  It flips
  23. -- only if all these bits, taken together, match the pattern 10* (a one
  24. -- followed by any number of zeros).
  25.  
  26. -- Almost every non-imaginary bit has a component instance that sets the
  27. -- bit based on the values of the lower-order bits, as described above.
  28. -- The rules have to differ slightly for the most significant bit or else
  29. -- the counter would saturate at it's highest value, 1000...0.
  30.  
  31. architecture rtl of gray_counter is
  32.  
  33.     -- q contains all the values of the counter, plus the imaginary bit
  34.     -- (values are shifted to make room for the imaginary bit at q(0))
  35.     signal q  : std_logic_vector (8 downto 0);
  36.    
  37.     -- no_ones_below(x) = 1 iff there are no 1's in q below q(x)
  38.     signal no_ones_below  : std_logic_vector (8 downto 0);
  39.    
  40.     -- q_msb is a modification to make the msb logic work
  41.     signal q_msb : std_logic;
  42.  
  43. begin
  44.  
  45.     q_msb <= q(7) or q(8);
  46.    
  47.     process(clk, reset, enable)
  48.     begin
  49.    
  50.         if(reset = '1') then
  51.        
  52.             -- Resetting involves setting the imaginary bit to 1
  53.             q(0) <= '1';
  54.             q(8 downto 1) <= (others => '0');
  55.        
  56.         elsif(rising_edge(clk) and enable='1') then
  57.        
  58.             -- Toggle the imaginary bit
  59.             q(0) <= not q(0);
  60.            
  61.             for i in 1 to 8 loop
  62.            
  63.                 -- Flip q(i) if lower bits are a 1 followed by all 0's
  64.                 q(i) <= q(i) xor (q(i-1) and no_ones_below(i-1));
  65.            
  66.             end loop;  -- i
  67.            
  68.             q(8) <= q(8) xor (q_msb and no_ones_below(7));
  69.            
  70.         end if;
  71.        
  72.     end process;
  73.    
  74.     -- There are never any 1's beneath the lowest bit
  75.     no_ones_below(0) <= '1';
  76.    
  77.     process(q, no_ones_below)
  78.     begin
  79.         for j in 1 to 8 loop
  80.             no_ones_below(j) <= no_ones_below(j-1) and not q(j-1);
  81.         end loop;
  82.     end process;
  83.    
  84.     -- Copy over everything but the imaginary bit
  85.     gray_count <= q(8 downto 1);
  86.    
  87. end rtl;
Advertisement
Add Comment
Please, Sign In to add comment
Advertisement