logic.vhdl

library ieee;
use ieee.std_logic_1164.all;

--Description interface the system
entity logic is
  port (
    I1: in std_ulogic; --first_input
    I2: in std_ulogic; --second_input
    I3: in std_ulogic; --second_input
    I4: in std_ulogic; --second_input
    I5: in std_ulogic; --second_input
    Q1: out std_ulogic; --direct outputs
    Q2: out std_ulogic; --inverse outputs
    Q3: out std_ulogic; --inverse outputs
    Q4: out std_ulogic; --inverse outputs
    TT2: out std_ulogic --inverse outputs
  );
end logic;

--Description behavior the system
architecture logic_behavior of logic is
  constant T1 : time := 2000 ms;
  constant T2 : time := 5000 ms;
  constant T3 : time := 7000 ms;

  signal Q1_2: std_logic;

  signal Q4_I1: std_logic;
  signal Q4_I2: std_logic;
  signal Q4_I3: std_logic;

  signal TT2_I: std_logic := '0';

begin
  Q1_2 <= (I1 and I2 and I3) or (I3 and I4 and I5) after T2;
  --TT2 <= '0' after 0 ms, '1' after T2;
  --if (TT2_I = '0') then
    --TT2 <= '0';
  --else
    --TT2 <= '1';
  --end if;
  Q1 <= Q1_2; --write direct output
  Q2 <= (not Q1_2); --write inverse output
  Q3 <= (not I1) or (not I2) or (not I3) or (not I4) after T3;

  Q4_I1 <= I1 after T1;
  Q4_I2 <= I2 after T2;
  Q4_I3 <= I3 after T3;
  Q4 <= Q4_I1 or Q4_I2 or Q4_I3;
end logic_behavior;