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logic.vhdl

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  1. library ieee;
  2. use ieee.std_logic_1164.all;
  3.  
  4. --Description interface the system
  5. entity logic is
  6.   port (
  7.     I1: in std_ulogic; --first_input
  8.     I2: in std_ulogic; --second_input
  9.     I3: in std_ulogic; --second_input
  10.     I4: in std_ulogic; --second_input
  11.     I5: in std_ulogic; --second_input
  12.     Q1: out std_ulogic; --direct outputs
  13.     Q2: out std_ulogic; --inverse outputs
  14.     Q3: out std_ulogic; --inverse outputs
  15.     Q4: out std_ulogic; --inverse outputs
  16.     TT2: out std_ulogic --inverse outputs
  17.   );
  18. end logic;
  19.  
  20. --Description behavior the system
  21. architecture logic_behavior of logic is
  22.   constant T1 : time := 2000 ms;
  23.   constant T2 : time := 5000 ms;
  24.   constant T3 : time := 7000 ms;
  25.  
  26.   signal Q1_2: std_logic;
  27.  
  28.   signal Q4_I1: std_logic;
  29.   signal Q4_I2: std_logic;
  30.   signal Q4_I3: std_logic;
  31.  
  32.   signal TT2_I: std_logic := '0';  
  33.  
  34. begin
  35.   Q1_2 <= (I1 and I2 and I3) or (I3 and I4 and I5) after T2;   
  36.   --TT2 <= '0' after 0 ms, '1' after T2;
  37.   --if (TT2_I = '0') then
  38.     --TT2 <= '0';
  39.   --else
  40.     --TT2 <= '1';
  41.   --end if;
  42.   Q1 <= Q1_2; --write direct output
  43.   Q2 <= (not Q1_2); --write inverse output
  44.   Q3 <= (not I1) or (not I2) or (not I3) or (not I4) after T3;
  45.  
  46.   Q4_I1 <= I1 after T1;
  47.   Q4_I2 <= I2 after T2;
  48.   Q4_I3 <= I3 after T3;
  49.   Q4 <= Q4_I1 or Q4_I2 or Q4_I3;
  50. end logic_behavior;
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