kolprem_buzzer.c

/*
 * kolprem_buzzer.c
 *
 * Created: 2019-02-06 10:25:48
 * Author : a

 Buzzer connected to PB0:PA4
 INPUTS:
 6  PA5 AIN5 - main input
 7  PA6 AIN6
 8  PA7 AIN7
 9  PB5 AIN8
 10 PB4 AIN9 (TXD)

 Workflow:
 The MCU monitors the AIN5 analog input, and when it detects a rising edge defined by thershold levels low_tsh and high_tsh,
 it activates buzzer for 1 second (generating ~3.3kHz square wave frequency on pins PB0 & PA4).



 */
#define F_CPU   32000UL

#include <avr/io.h>
#include <util/delay.h>
#include <avr/interrupt.h>
#include <avr/sleep.h>
#include <avr/eeprom.h>
#include <avr/lock.h>

LOCKBITS = (LB_RWLOCK_gc);



volatile uint8_t start_signal = 1; //1 after rising edge
volatile uint8_t lastState = 0, currentState = 0;
const uint8_t low_tsh=(uint8_t)256.0*0.8/5.0, high_tsh=(uint8_t)256.0*1.2/5.0;
const char info[] EEMEM = "Kolprem bnuzzer REV 02. Analog readout. Rising-edge trigger above 1.2V.";
extern void ccp_write_io(void *addr, uint8_t value);


int8_t DIGITAL_GLUE_LOGIC_0_init()
{

    // Enable Protected register, peripheral must be disabled (ENABLE=0, in TCD.LUT0CTRLA).

    // CCL.SEQCTRL0 = CCL_SEQSEL_DISABLE_gc /* Sequential logic disabled */;

    CCL.TRUTH0 = 1; /* Truth 0: 1 */

    // CCL.LUT0CTRLC = CCL_INSEL2_MASK_gc /* Masked input */;

    CCL.LUT0CTRLB = CCL_INSEL0_TCA0_gc /* TCA0 WO0 input source */
    | CCL_INSEL1_MASK_gc /* Masked input */;

    CCL.LUT0CTRLA = 0 << CCL_CLKSRC_bp       /* Clock Source Selection: disabled */
    | CCL_EDGEDET_DIS_gc     /* Edge detector is disabled */
    | CCL_FILTSEL_DISABLE_gc /* Filter disabled */
    | 1 << CCL_ENABLE_bp     /* LUT Enable: enabled */
    | 1 << CCL_OUTEN_bp;     /* Output Enable: enabled */

    // CCL.TRUTH1 = 0; /* Truth 1: 0 */

    // CCL.LUT1CTRLC = CCL_INSEL2_MASK_gc /* Masked input */;

    // CCL.LUT1CTRLB = CCL_INSEL0_MASK_gc /* Masked input */
    //       | CCL_INSEL1_MASK_gc /* Masked input */;

    CCL.LUT1CTRLA = 0 << CCL_CLKSRC_bp       /* Clock Source Selection: disabled */
    | CCL_EDGEDET_DIS_gc     /* Edge detector is disabled */
    | CCL_FILTSEL_DISABLE_gc /* Filter disabled */
    | 0 << CCL_ENABLE_bp     /* LUT Enable: disabled */
    | 1 << CCL_OUTEN_bp;     /* Output Enable: enabled */

    CCL.CTRLA = 1 << CCL_ENABLE_bp      /* Enable: enabled */
    | 0 << CCL_RUNSTDBY_bp; /* Run in Standby: disabled */

    return 0;
}
/************************************************************************/
/* CLK init CPU_CLK=32Khz                                                                     */
/************************************************************************/
int8_t CLKCTRL_init()
{

    // ccp_write_io((void*)&(CLKCTRL.OSC32KCTRLA),0 << CLKCTRL_RUNSTDBY_bp /* Run standby: disabled */);

    // ccp_write_io((void*)&(CLKCTRL.XOSC32KCTRLA),CLKCTRL_CSUT_1K_gc /* 1k cycles */
    //       | 0 << CLKCTRL_ENABLE_bp /* Enable: disabled */
    //       | 0 << CLKCTRL_RUNSTDBY_bp /* Run standby: disabled */
    //       | 0 << CLKCTRL_SEL_bp /* Select: disabled */);

    // ccp_write_io((void*)&(CLKCTRL.OSC20MCTRLA),0 << CLKCTRL_RUNSTDBY_bp /* Run standby: disabled */);

    ccp_write_io((void *)&(CLKCTRL.MCLKCTRLB),
    CLKCTRL_PDIV_6X_gc /* 6 */
    | 0 << CLKCTRL_PEN_bp /* Prescaler enable: disabled */);

    ccp_write_io((void *)&(CLKCTRL.MCLKCTRLA),
    CLKCTRL_CLKSEL_OSCULP32K_gc /* 32KHz Internal Ultra Low Power Oscillator (OSCULP32K) */
    | 0 << CLKCTRL_CLKOUT_bp /* System clock out: disabled */);

    /* wait for system oscillator changing to finish */
    while (CLKCTRL.MCLKSTATUS & CLKCTRL_SOSC_bm) {
    }

    // ccp_write_io((void*)&(CLKCTRL.MCLKLOCK),0 << CLKCTRL_LOCKEN_bp /* lock enable: disabled */);

    return 0;
}

void GPIO_init(void)
{
    /* Buzzer PB0:PA4 */
    /* INPUT PA5 AIN5 */
    /* GPIO */
    PORTA_OUTSET = PIN4_bm;
    PORTB_DIRSET = PIN0_bm;

    //PORTA_PIN5CTRL = PORT_PULLUPEN_bm;
    DIGITAL_GLUE_LOGIC_0_init();
}

void TCA0_init(void){
    /* Timer A configuration - audio freq. output */
    TCA0_SINGLE_CTRLA = TCA_SINGLE_ENABLE_bm;
    TCA0_SINGLE_CTRLB = TCA_SINGLE_WGMODE_FRQ_gc|TCA_SINGLE_CMP0_bm;
    TCA0_SINGLE_CMP0 = 4; // 550 = 3Khz @ CPU_CLK = 3.3MHz; 4 = 3.3KHz @ CPU_CLK=32Khz

    TCA0_SINGLE_CNT = 0;
    TCA0_SINGLE_CTRLA = 0;
    /* Timer B configuration - pulse freq. output */
    TCB0_CTRLA = TCB_ENABLE_bm;
    TCB0_CTRLB = 0;


}

void ADC_init(void){
    ADC0_CTRLA = ADC_RUNSTBY_bm|ADC_RESSEL_bm|ADC_ENABLE_bm;
    ADC0_CTRLB = ADC_SAMPNUM_ACC4_gc;
    ADC0_CTRLC = ADC_REFSEL_VDDREF_gc|ADC_PRESC_DIV2_gc;
    ADC0_MUXPOS = ADC_MUXPOS_AIN5_gc;
    ADC0_INTCTRL = ADC_RESRDY_bm;
    ADC0_COMMAND = ADC_STCONV_bm;

}

void signal_on(void){
    TCA0_SINGLE_CTRLA = TCA_SINGLE_ENABLE_bm;
}

void signal_off(void){
    TCA0_SINGLE_CTRLA = 0;
}

int main(void)
{
    sei();
    GPIO_init();
    TCA0_init();
    signal_off();
    CLKCTRL_init();
    ADC_init();

    while (1)
    {

        if(start_signal){
            signal_on();
            _delay_ms(1000);
            signal_off();
            _delay_ms(1000);
            start_signal = 0;
            //go to idle sleep
            set_sleep_mode(SLEEP_MODE_STANDBY);
            sleep_enable();
            sleep_cpu();
        }
    }//while(1)
}


/************************************************************************/
/* ADC ISR                                                              */
/************************************************************************/
ISR(ADC0_RESRDY_vect){

    lastState = currentState;
    //calculate current state
    if (ADC0_RES > high_tsh)
    {
        currentState = 1;
    }
    if (ADC0_RES < low_tsh)
    {
        currentState = 0;
    }

    //rising edge detection
    if ((currentState ==1) && (lastState == 0))
    {
        start_signal = 1;
    }
    //start next aquisition
    ADC0_INTFLAGS = ADC_RESRDY_bm;
    ADC0_COMMAND = ADC_STCONV_bm;
}