fulladder1bittest

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-- Company:
-- Engineer:
--
-- Create Date:   16:04:53 09/23/2019
-- Design Name:
-- Module Name:   C:/Users/cgtucker/CompOrg/Lab2Attempt2/full_adder_1bit_test.vhd
-- Project Name:  Lab2Attempt2
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: full_adder_1bit
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY full_adder_1bit_test IS
END full_adder_1bit_test;

ARCHITECTURE behavior OF full_adder_1bit_test IS

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT full_adder_1bit
    PORT(
         Cin : IN  std_logic;
         A : IN  std_logic;
         B : IN  std_logic;
         Sout : OUT  std_logic;
         Cout : OUT  std_logic
        );
    END COMPONENT;


   --Inputs
   signal Cin : std_logic := '0';
   signal A : std_logic := '0';
   signal B : std_logic := '0';

    --Outputs
   signal Sout : std_logic;
   signal Cout : std_logic;
   -- No clocks detected in port list. Replace <clock> below with
   -- appropriate port name

BEGIN

    -- Instantiate the Unit Under Test (UUT)
   uut: full_adder_1bit PORT MAP (
          Cin => Cin,
          A => A,
          B => B,
          Sout => Sout,
          Cout => Cout
        );

   -- Clock process definitions


   -- Stimulus process
   stim_proc: process
   begin
      -- hold reset state for 100 ns.
      wait for 100 ns;

      Cin <= '0';
      A <= '0';
      B <= '1';
      wait for 100 ns;

      Cin <= '0';
      A <= '1';
      B <= '0';
      wait for 100 ns;


      Cin <= '0';
      A <= '1';
      B <= '1';
      wait for 100 ns;

      Cin <= '1';
      A <= '0';
      B <= '0';
      wait for 100 ns;

      Cin <= '1';
      A <= '0';
      B <= '1';
      wait for 100 ns;

      Cin <= '1';
      A <= '1';
      B <= '0';
      wait for 100 ns;

      Cin <= '1';
      A <= '1';
      B <= '1';
      wait for 100 ns;

      -- insert stimulus here

      wait;
   end process;

END;